Chisel

FPGABackend

class FPGABackend extends VerilogBackend

Linear Supertypes
VerilogBackend, Backend, AnyRef, Any
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  1. FPGABackend
  2. VerilogBackend
  3. Backend
  4. AnyRef
  5. Any
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Instance Constructors

  1. new FPGABackend()

Value Members

  1. final def !=(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  2. final def !=(arg0: Any): Boolean

    Definition Classes
    Any

  3. final def ##(): Int

    Definition Classes
    AnyRef → Any

  4. final def ==(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  5. final def ==(arg0: Any): Boolean

    Definition Classes
    Any

  6. val analyses: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  7. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  8. def asValidName(name: String): String

    Definition Classes
    Backend

  9. def assignClockAndResetToModules: Unit

    Definition Classes
    Backend

  10. def checkPorts(topC: Module): Unit

    Definition Classes
    Backend

  11. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  12. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Definition Classes
    Backend

  13. val compIndices: HashMap[String, Int]

    Definition Classes
    VerilogBackend

  14. def compile(c: Module, flags: String): Unit

    Definition Classes
    VerilogBackend → Backend

  15. def connectResets: Unit

    Definition Classes
    Backend

  16. def createClkDomain(root: Node, walked: ArrayBuffer[Node]): Unit

    Definition Classes
    Backend

  17. def createOutputFile(name: String): FileWriter

    Definition Classes
    Backend

  18. def depthString(depth: Int): String

    Definition Classes
    Backend

  19. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend

  20. def elaborate(c: Module): Unit

    Definition Classes
    VerilogBackend → Backend

  21. def emitChildren(top: Module, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes
    VerilogBackend

  22. def emitDec(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend → Backend

  23. def emitDecBase(node: Node): String

    Definition Classes
    VerilogBackend

  24. def emitDecs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  25. def emitDef(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend → Backend

  26. def emitDef(c: Module): String

    Definition Classes
    VerilogBackend

  27. def emitDefs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  28. def emitModuleText(c: Module): String

    Definition Classes
    VerilogBackend

  29. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes
    VerilogBackend

  30. def emitRef(node: Node): String

    Definition Classes
    VerilogBackend → Backend

  31. def emitRef(c: Module): String

    Definition Classes
    Backend

  32. def emitReg(node: Node): String

    Definition Classes
    FPGABackend → VerilogBackend

  33. def emitRegs(c: Module): StringBuilder

    Definition Classes
    VerilogBackend

  34. def emitTmp(node: Node): String

    Definition Classes
    VerilogBackend → Backend

  35. def emitWidth(node: Node): String

    Definition Classes
    VerilogBackend

  36. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes
    Backend

  37. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  38. def equals(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  39. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes
    Backend

  40. def extractClassName(comp: Module): String

    Definition Classes
    Backend

  41. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  42. def flushModules(out: FileWriter, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes
    VerilogBackend

  43. val flushedTexts: HashSet[String]

    Definition Classes
    VerilogBackend

  44. def fullyQualifiedName(m: Node): String

    Definition Classes
    Backend

  45. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes
    Backend

  46. def gatherClocksAndResets: Unit

    Definition Classes
    Backend

  47. def genHarness(c: Module, name: String): Unit

    Definition Classes
    VerilogBackend

  48. def genIndent(x: Int): String

    Attributes
    protected
    Definition Classes
    Backend

  49. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  50. def hashCode(): Int

    Definition Classes
    AnyRef → Any

  51. def initializeDFS: Stack[Node]

    Definition Classes
    Backend

  52. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Module.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes
    Backend

  53. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  54. def isMultiWrite(m: Mem[_]): Boolean

  55. val keywords: HashSet[String]

    Definition Classes
    VerilogBackend → Backend

  56. def levelChildren(root: Module): Unit

    Definition Classes
    Backend

  57. val memConfs: HashMap[String, String]

    Definition Classes
    VerilogBackend

  58. def nameAll(root: Module): Unit

    Definition Classes
    Backend

  59. def nameChildren(root: Module): Unit

    Definition Classes
    Backend

  60. def nameRsts: Unit

    Definition Classes
    Backend

  61. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  62. final def notify(): Unit

    Definition Classes
    AnyRef

  63. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  64. val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  65. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes
    protected
    Definition Classes
    Backend

  66. def pruneNodes: Unit

    Definition Classes
    Backend

  67. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes
    Backend

  68. def romStyle: String

    Definition Classes
    FPGABackend → VerilogBackend

  69. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  70. def toString(): String

    Definition Classes
    AnyRef → Any

  71. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes
    Backend

  72. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  73. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  74. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  75. def writeMap(m: Mem[_], exclude: Int = 1): Seq[String]

  76. def writen(m: MemWrite): Int

Inherited from VerilogBackend

Inherited from Backend

Inherited from AnyRef

Inherited from Any

Ungrouped