!=

Bits Dbl Flo SInt

##

Bits Data Node

%

Bits Dbl Flo Num SInt UInt SFix UFix

&

Bits

&&

Bool

*

Bits Clock Dbl Flo Num SInt UInt SFix UFix

+

Bits Bundle Dbl Flo Num SInt UInt SFix UFix

+=

Bundle

-

Bits Dbl Flo Num SInt UInt SFix UFix

-=

Bundle

/

Bits Clock Dbl Flo Num SInt UInt SFix UFix

::

Mux

:=

Bits Bool Bundle Data Dbl Flo SInt UInt Vec SFix UFix

<

Dbl Flo Num SInt UInt SFix UFix

<<

SInt UInt SFix UFix

<=

Dbl Flo Num SInt UInt SFix UFix

<>

Bits Bundle Module Node Vec

===

Bits Data Dbl Flo SInt UInt

>

Dbl Flo Num SInt UInt SFix UFix

>=

Dbl Flo Num SInt UInt SFix UFix

>>

SInt UInt SFix UFix

?

SInt UInt

^

Bits

^^

Node

|

Bits

||

Bool