CounterVBackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. def addPin(m: Module, pin: Data, name: String): Unit

   Definition Classes

   CounterBackend

7. def addReg(m: Module, outType: Bits, name: String = "", updates: Map[Bool, Node] = Map()): Unit

   Definition Classes

   CounterBackend

8. val analyses: ArrayBuffer[(Module) ⇒ Unit]

   Definition Classes

   Backend

9. final def asInstanceOf[T0]: T0

   Definition Classes

   Any

10. def asValidName(name: String): String

    Definition Classes

    Backend

11. def assignClockAndResetToModules: Unit

    Definition Classes

    Backend

12. def backannotationAnalyses: Unit

    Definition Classes

    Backend

13. def backannotationTransforms: Unit

    Definition Classes

    CounterBackend → Backend

14. def checkPorts(topC: Module): Unit

    Definition Classes

    Backend

15. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

16. def collectNodesIntoComp(dfsStack: Stack[Node]): Unit

    Definition Classes

    Backend

17. val compIndices: HashMap[String, Int]

    Definition Classes

    VerilogBackend

18. def compile(c: Module, flags: String): Unit

    Definition Classes

    VerilogBackend → Backend

19. def connectConsumers(input: Node, via: Node): Unit

    Definition Classes

    CounterBackend

20. def connectDaisyPins(c: Module): Unit

    Definition Classes

    CounterBackend

21. def connectResets: Unit

    Definition Classes

    Backend

22. val counterCopy: HashMap[Module, Bool]

    Definition Classes

    CounterBackend

23. var counterIdx: Int

    Definition Classes

    CounterBackend

24. val counterRead: HashMap[Module, Bool]

    Definition Classes

    CounterBackend

25. def createClkDomain(root: Node, walked: ArrayBuffer[Node]): Unit

    Definition Classes

    Backend

26. def createOutputFile(name: String): FileWriter

    Definition Classes

    Backend

27. val daisyCtrls: HashMap[Module, Bits]

    Definition Classes

    CounterBackend

28. val daisyIns: HashMap[Module, UInt]

    Definition Classes

    CounterBackend

29. val daisyOuts: HashMap[Module, DecoupledIO[UInt]]

    Definition Classes

    CounterBackend

30. def decoupleTarget(c: Module): Unit

    Definition Classes

    CounterBackend

31. val decoupledPins: HashMap[Node, Bits]

    Definition Classes

    CounterBackend

32. def depthString(depth: Int): String

    Definition Classes

    Backend

33. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

34. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

35. def emitAssert(a: Assert): String

    Definition Classes

    VerilogBackend

36. def emitChildren(top: Module, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

37. def emitCounterIdx: Int

    Definition Classes

    CounterBackend

38. def emitDec(node: Node): String

    Definition Classes

    VerilogBackend → Backend

39. def emitDecBase(node: Node): String

    Definition Classes

    VerilogBackend

40. def emitDecs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

41. def emitDef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

42. def emitDef(c: Module): String

    Definition Classes

    VerilogBackend

43. def emitDefs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

44. def emitInit(node: Node): String

    Definition Classes

    VerilogBackend

45. def emitInits(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

46. def emitModuleText(c: Module): String

    Definition Classes

    VerilogBackend

47. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes

    VerilogBackend

48. def emitPrintf(p: Printf): String

    Definition Classes

    VerilogBackend

49. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

50. def emitRef(c: Module): String

    Definition Classes

    Backend

51. def emitReg(node: Node): String

    Definition Classes

    VerilogBackend

52. def emitRegs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

53. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

54. def emitWidth(node: Node): String

    Definition Classes

    VerilogBackend

55. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    Backend

56. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

57. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

58. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

59. def extractClassName(comp: Module): String

    Definition Classes

    Backend

60. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

61. val firedPins: HashMap[Module, Bool]

    Definition Classes

    CounterBackend

62. def flushModules(out: FileWriter, defs: HashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes

    VerilogBackend

63. val flushedTexts: HashSet[String]

    Definition Classes

    VerilogBackend

64. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

65. def gatherChildren(root: Module): ArrayBuffer[Module]

    Definition Classes

    Backend

66. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

67. def genHarness(c: Module, name: String): Unit

    Definition Classes

    VerilogBackend

68. def genIndent(x: Int): String

    Attributes

    protected

    Definition Classes

    Backend

69. def generateCounters(c: Module): Unit

    Definition Classes

    CounterBackend

70. def generateDaisyChains(c: Module): Unit

    Definition Classes

    CounterBackend

71. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

72. def getPseudoPath(c: Module, delim: String = "/"): String

    Definition Classes

    Backend

73. def getSignalPathName(n: Node, delim: String = "/", isRealName: Boolean = false): String

    Definition Classes

    Backend

74. def hashCode(): Int

    Definition Classes

    AnyRef → Any

75. def initBackannotation: Unit

    Definition Classes

    Backend

76. def initializeDFS: Stack[Node]

    Definition Classes

    Backend

77. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Module.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

78. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

79. val keywords: HashSet[String]

    Definition Classes

    VerilogBackend → Backend

80. def levelChildren(root: Module): Unit

    Definition Classes

    Backend

81. val memConfs: HashMap[String, String]

    Definition Classes

    VerilogBackend

82. def nameAll(root: Module): Unit

    Definition Classes

    Backend

83. def nameChildren(root: Module): Unit

    Definition Classes

    Backend

84. def nameRsts: Unit

    Definition Classes

    Backend

85. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

86. final def notify(): Unit

    Definition Classes

    AnyRef

87. final def notifyAll(): Unit

    Definition Classes

    AnyRef

88. val preElaborateTransforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

89. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

90. def pruneNodes: Unit

    Definition Classes

    Backend

91. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes

    Backend

92. def romStyle: String

    Definition Classes

    VerilogBackend

93. def setPseudoNames(c: Module): Unit

    Definition Classes

    Backend

94. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

95. def toString(): String

    Definition Classes

    AnyRef → Any

96. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

97. final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

98. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

99. final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

100. def wirePin(pin: Data, input: Node): Unit

     Definition Classes

     CounterBackend

101. def writeOutGraph(c: Module): Unit

     Definition Classes

     Backend