class
Reg extends Delay with proc
Instance Constructors
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new
Reg()
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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def
<>(src: Node): Unit
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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def
^^(src: Node): Unit
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def
addConsumers(): Unit
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final
def
asInstanceOf[T0]: T0
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def
assign(src: Node): Unit
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var
assigned: Boolean
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def
bitSet(off: UInt, dat: UInt): UInt
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def
canCSE: Boolean
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lazy val
chiselName: String
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var
clock: Clock
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def
clone(): AnyRef
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var
cntrIdx: Int
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var
component: Module
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def
componentOf: Module
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val
consumers: ArrayBuffer[Node]
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var
counter: Bits
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def
dblLitValue: Double
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def
dblValue: Double
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var
depth: Int
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var
driveRand: Boolean
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def
emitIndex(): Int
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var
enable: Bool
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var
enableIndex: Int
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def
enableSignal: Node
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(that: Any): Boolean
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def
equalsForCSE(x: Node): Boolean
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def
extract(b: Bundle): List[Node]
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def
extract(widths: Array[Int]): List[UInt]
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def
finalize(): Unit
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var
flattened: Boolean
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def
floLitValue: Float
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def
floValue: Float
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def
forceMatchingWidths: Unit
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var
genError: Boolean
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def
genMuxes(default: Node): Unit
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def
genMuxes(default: Node, others: Seq[(Bool, Node)]): Unit
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final
def
getClass(): Class[_]
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def
getNode(): Node
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def
getWidth(): Int
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val
hashCode: Int
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def
hashCodeForCSE: Int
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var
index: Int
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def
infer: Boolean
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var
inferCount: Int
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var
inferWidth: (Node) ⇒ Int
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def
init: Node
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def
init(n: String, w: Int, ins: Node*): Node
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def
init(n: String, width: (Node) ⇒ Int, ins: Node*): Node
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def
initOf(n: String, width: (Node) ⇒ Int, ins: Iterable[Node]): Node
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val
inputs: ArrayBuffer[Node]
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def
isByValue: Boolean
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var
isClkInput: Boolean
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var
isEnable: Boolean
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var
isFixedWidth: Boolean
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def
isInObject: Boolean
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def
isInVCD: Boolean
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final
def
isInstanceOf[T0]: Boolean
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def
isIo: Boolean
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def
isIo_=(isIo: Boolean): Unit
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def
isLit: Boolean
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var
isPrintArg: Boolean
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def
isRamWriteInput(i: Node): Boolean
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def
isReg: Boolean
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var
isReset: Boolean
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var
isScanArg: Boolean
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var
isTypeNode: Boolean
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def
isUpdate: Boolean
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def
isUsedByRam: Boolean
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var
isWidthWalked: Boolean
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var
line: StackTraceElement
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def
litValue(default: BigInt = BigInt(-1)): BigInt
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def
matchWidth(w: Int): Node
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def
maxNum: BigInt
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def
maybeFlatten: Seq[Node]
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def
minNum: BigInt
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val
muxes: HashMap[(Bool, Node), Node]
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var
name: String
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def
nameIt(path: String, isNamingIo: Boolean): Unit
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def
nameOpt: String
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var
named: Boolean
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final
def
ne(arg0: AnyRef): Boolean
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def
next: Node
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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var
pName: String
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def
printTree(writer: PrintStream, depth: Int = 4, indent: String = ""): Unit
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def
procAssign(src: Node): Unit
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var
prune: Boolean
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var
pseudoMux: Node
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def
removeTypeNodes(): Unit
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var
sccIndex: Int
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var
sccLowlink: Int
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def
setIsClkInput: Unit
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def
setName(n: String): Unit
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def
setPseudoName(path: String, isNamingIo: Boolean): Unit
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var
shadow: Bits
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var
stack: Array[StackTraceElement]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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def
traceNode(c: Module, stack: Stack[() ⇒ Any]): Any
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def
traceableNodes: Array[Node]
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def
update(x: Node): Unit
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val
updates: ListBuffer[(Bool, Node)]
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def
value: BigInt
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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var
walked: Boolean
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def
width: Int
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var
width_: Int
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def
width_=(w: Int): Unit
Inherited from AnyRef
Inherited from Any
