Chisel
Hardware module that is used to sequence n producers into 1 consumer.
Base class for built-in Chisel types Bits and SInt.
Defines a collection of datum of different types into a single coherent whole.
*Data* is part of the *Node* Composite Pattern class hierarchy.
*Data* is part of the *Node* Composite Pattern class hierarchy. It is the root of the type system which includes composites (Bundle, Vec) and atomic types (UInt, SInt, etc.).
Instances of Data are meant to help with construction and correctness of a logic graph. They will trimmed out of the graph before a *Backend* generates target code.
Stores the actual value of a scala literal as a string.
Stores the actual value of a scala literal as a string. This class should not end-up being instantiated directly in user code.
*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.wikipedia.org/wiki/Composite_pattern).
*Node* defines the root class of the class hierarchy for a [Composite Pattern](http://en.wikipedia.org/wiki/Composite_pattern).
A digital logic graph is encoded as adjacency graph where instances of *Node* describe vertices and *inputs*, *consumers* member fields are used to traverse the directed graph respectively backward (from output to input) and forward (from input to output).
Hardware module that is used to sequence n producers into 1 consumer.
Hardware module that is used to sequence n producers into 1 consumer. Producers are chosen in round robin order.
Example usage: val arb = new RRArbiter(2, UInt()) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out
This Singleton implements a log4j compatible interface.
This Singleton implements a log4j compatible interface. It is used through out the Chisel package to report errors and warnings detected at runtime.
Adds a ready-valid handshaking protocol to any interface.
Adds a ready-valid handshaking protocol to any interface. The standard used is that the consumer uses the flipped interface.
linear feedback shift register
*seqRead* means that if a port tries to read the same address that another port is writing to in the same cycle, the read data is random garbage (from a LFSR, which returns "1" on its first invocation).
Builds a Mux tree out of the input signal vector using a one hot encoded select signal.
Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree.
Does the inverse of UIntToOH.
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter.
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.
Example usage: val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq
Returns the number of bits set (i.e value is 1) in the input signal.
Returns the bit position of the trailing 1 in the input vector with the assumption that multiple bits of the input bit vector can be set
Returns a bit vector in which only the least-significant 1 bit in the input vector, if any, is set.
Builds a Mux tree under the assumption that multiple select signals can be enabled.
Builds a Mux tree under the assumption that multiple select signals can be enabled. Priority is given to the first select signal.
Returns the output of the Mux tree.
Generic hardware queue.
Generic hardware queue. Required parameter entries controls the depth of the queues. The width of the queue is determined from the inputs.
Example usage: val q = new Queue(UInt(), 16) q.io.enq <> producer.io.out consumer.io.in <> q.io.deq
Litte/big bit endian convertion: reverse the order of the bits in a UInt.
Returns the n-cycle delayed version of the input signal.
Returns the one hot encoding of the input UInt.
Adds a valid protocol to any interface.
Adds a valid protocol to any interface. The standard used is that the consumer uses the flipped interface.
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter.
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter. That execution tree is simplified by aggregating all calls which are not constructors of a Module instance into the parent which is. The simplified tree (encoded through _Driver.children_) forms the basis of the generated verilog. Each node in the simplified execution tree is a _Module_ instance from which a verilog module is textually derived. As an optimization, _Backend_ classes output modules which are textually equivalent only once and update a _Module_ instance's _moduleName_ accordingly.
Hardware module that is used to sequence n producers into 1 consumer. Priority is given to lower producer
Example usage: val arb = Module(new Arbiter(2, UInt())) arb.io.in(0) <> producer0.io.out arb.io.in(1) <> producer1.io.out consumer.io.in <> arb.io.out