Driver

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
var allocateOnlyNeededShadowRegisters: Boolean
def appendString(s1: Option[String], s2: Option[String]): String
def apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T], wrapped: Boolean): T
def apply[T <: Module](args: Array[String], gen: () ⇒ T, wrapped: Boolean): T
final def asInstanceOf[T0]: T0

Definition Classes
Any
var backend: Backend
def bfs(visit: (Node) ⇒ Unit): Unit
val blackboxes: ArrayBuffer[BlackBox]
var chiselConfigClassName: Option[String]
var chiselConfigDump: Boolean
var chiselConfigMode: Option[String]
val chiselOneHotBitMap: HashMap[(Bits, Int), Bool]
val chiselOneHotMap: HashMap[(UInt, Int), UInt]
var chiselProjectName: Option[String]
val clocks: ArrayBuffer[Clock]
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compStack: Stack[Module]
var compileInitializationUnoptimized: Boolean
val components: ArrayBuffer[Module]
def createOutputFile(name: String): FileWriter

Definition Classes
FileSystemUtilities
def dfs(visit: (Node) ⇒ Unit): Unit
var dontFindCombLoop: Boolean
var dumpTestInput: Boolean
def elapsedTime: Long
var emitTempNodes: Boolean
def ensureDir(dir: String): String

Ensures a directory *dir* exists on the filesystem.
Ensures a directory *dir* exists on the filesystem.

Definition Classes
FileSystemUtilities
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def getArg(s: String, i: Int): String
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
var getLineNumbers: Boolean
var hasMem: Boolean
var hasSRAM: Boolean
def hashCode(): Int

Definition Classes
AnyRef → Any
def idfs(visit: (Node) ⇒ Unit): Unit
var implicitClock: Clock
val implicitReset: Bool
var includeArgs: List[String]
def initChisel(args: Array[String]): Unit
var isAssert: Boolean
var isCSE: Boolean
var isCheckingPorts: Boolean
def isCommandAvailable(cmd: String): Boolean
var isCompiling: Boolean
var isDebug: Boolean
var isDebugMem: Boolean
var isGenHarness: Boolean
var isInGetWidth: Boolean
var isInlineMem: Boolean
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
var isIoDebug: Boolean
var isReportDims: Boolean
var isSupportW0W: Boolean
var isTesting: Boolean
var isVCD: Boolean
var isVCDMem: Boolean
var isVCDinline: Boolean
lazy val isVCSAvailable: Boolean
var lineLimitFunctions: Int
var minimumLinesPerFile: Int
var modAdded: Boolean
var modStackPushed: Boolean
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val nodes: ArrayBuffer[Node]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val orderedNodes: ArrayBuffer[Node]
val parStack: Stack[Parameters]
var parallelMakeJobs: Int
var partitionIslands: Boolean
val printStackStruct: ArrayBuffer[(Int, Module)]
var saveComponentTrace: Boolean
var saveConnectionWarnings: Boolean
def setTopComponent(mod: Module): Unit
var shadowRegisterInObject: Boolean
val sortedComps: ArrayBuffer[Module]
var sramMaxSize: Int
var stackIndent: Int
var startTime: Long
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
var targetDir: String
var testCommand: Option[String]
var testerSeed: Long
var testerSeedValid: Boolean
def toString(): String

Definition Classes
AnyRef → Any
var topComponent: Module
var useSimpleQueue: Boolean
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
var warnInputs: Boolean
var warnOutputs: Boolean

Related Doc: package Chisel

object Driver extends FileSystemUtilities

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var allocateOnlyNeededShadowRegisters: Boolean

def appendString(s1: Option[String], s2: Option[String]): String

def apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T], wrapped: Boolean): T

def apply[T <: Module](args: Array[String], gen: () ⇒ T, wrapped: Boolean): T

final def asInstanceOf[T0]: T0

var backend: Backend

def bfs(visit: (Node) ⇒ Unit): Unit

val blackboxes: ArrayBuffer[BlackBox]

var chiselConfigClassName: Option[String]

var chiselConfigDump: Boolean

var chiselConfigMode: Option[String]

val chiselOneHotBitMap: HashMap[(Bits, Int), Bool]

val chiselOneHotMap: HashMap[(UInt, Int), UInt]

var chiselProjectName: Option[String]

val clocks: ArrayBuffer[Clock]

def clone(): AnyRef

val compStack: Stack[Module]

var compileInitializationUnoptimized: Boolean

val components: ArrayBuffer[Module]

def createOutputFile(name: String): FileWriter

def dfs(visit: (Node) ⇒ Unit): Unit

var dontFindCombLoop: Boolean

var dumpTestInput: Boolean

def elapsedTime: Long

var emitTempNodes: Boolean

def ensureDir(dir: String): String

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

def getArg(s: String, i: Int): String

final def getClass(): Class[_]

var getLineNumbers: Boolean

var hasMem: Boolean

var hasSRAM: Boolean

def hashCode(): Int

def idfs(visit: (Node) ⇒ Unit): Unit

var implicitClock: Clock

val implicitReset: Bool

var includeArgs: List[String]

def initChisel(args: Array[String]): Unit

var isAssert: Boolean

var isCSE: Boolean

var isCheckingPorts: Boolean

def isCommandAvailable(cmd: String): Boolean

var isCompiling: Boolean

var isDebug: Boolean

var isDebugMem: Boolean

var isGenHarness: Boolean

var isInGetWidth: Boolean

var isInlineMem: Boolean

final def isInstanceOf[T0]: Boolean

var isIoDebug: Boolean

var isReportDims: Boolean

var isSupportW0W: Boolean

var isTesting: Boolean

var isVCD: Boolean

var isVCDMem: Boolean

var isVCDinline: Boolean

lazy val isVCSAvailable: Boolean

var lineLimitFunctions: Int

var minimumLinesPerFile: Int

var modAdded: Boolean

var modStackPushed: Boolean

final def ne(arg0: AnyRef): Boolean

val nodes: ArrayBuffer[Node]

final def notify(): Unit

final def notifyAll(): Unit

val orderedNodes: ArrayBuffer[Node]

val parStack: Stack[Parameters]

var parallelMakeJobs: Int

var partitionIslands: Boolean

val printStackStruct: ArrayBuffer[(Int, Module)]

var saveComponentTrace: Boolean