verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
verifyWireWrap (Chisel3) - verify assignment semantics (type-only nodes must be wire-wrapped)
- HashMap of source lines (and associated nodes) requiring Wire() wrapping.
the I/O for this module
Connect io with matching names for two modules
Add a clock to the module
Add a clock to the module
the clock to add
Add a default reset to the module
Add a submodule to this module
Add a submodule to this module
Add a pin with a name to the module
Add a pin with a name to the module
the I/O to add
A name for the pin
the pin connected to the reset signal or creates a new one if no such pin exists
Add an assertion in the code generated by a backend.
A breadth first search of the graph of nodes
the implied clock for this module
Insures a backend does not remove a signal because it is unreachable from the outputs.
A depth first search of the graph of nodes
A method to trace the graph of nodes backwards looking at inputs
A method to trace the graph of nodes backwards looking at inputs
Node to find bindings for
nodes which have node m binded as their input
The separator to use for the path name
the absolute path to a component instance from toplevel
the absolute path to a component instance from toplevel
Name of the module this component generates (defaults to class name).
Name of the instance.
Name of the instance.
named is used to indicate that name was set explicitly and should not be overriden
named is used to indicate that name was set explicitly and should not be overriden
Adds a printf to the module called each clock cycle
Adds a printf to the module called each clock cycle
A c style sting to print out eg) %d, %x
Nodes whos data values should be printed
the implied reset for this module
Set the declaration name of the module to be string 'n'
Set the name of this module to the string 'n'
Set the name of this module to the string 'n'
my.io.node.setName("MY_IO_NODE")
Get the I/O names and connections
A Module or block to logically divide a hardware design
This is the same construct as module in verilog Also see Module object