Class

Chisel

FPGABackend

Related Doc: package Chisel

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class FPGABackend extends VerilogBackend

class with no inline mem

Source
FPGA.scala
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Inherited
  1. FPGABackend
  2. VerilogBackend
  3. Backend
  4. FileSystemUtilities
  5. AnyRef
  6. Any
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Visibility
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Instance Constructors

  1. new FPGABackend()

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Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  4. val CC: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  5. val CCFLAGS: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  6. val CPPFLAGS: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  7. val CXX: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  8. val CXXFLAGS: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  9. val LDFLAGS: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  10. def W0Wtransform(): Unit

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    Definition Classes
    Backend
  11. def addBindings: Unit

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    Definition Classes
    Backend
  12. def addClocksAndResets: Unit

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    Definition Classes
    Backend
  13. def addDefaultResets: Unit

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    Definition Classes
    Backend
  14. val analyses: ArrayBuffer[(Module) ⇒ Unit]

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    Definition Classes
    Backend
  15. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any
  16. def asValidName(name: String): String

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    Definition Classes
    Backend
  17. def assignClockAndResetToModules: Unit

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    Definition Classes
    Backend
  18. def cc(dir: String, name: String, flags: String = "", isCC: Boolean = false): Unit

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    Definition Classes
    FileSystemUtilities
  19. def checkModuleResolution: Unit

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    Definition Classes
    Backend
  20. def checkPorts: Unit

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    Definition Classes
    Backend
  21. val chiselENV: String

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    Attributes
    protected
    Definition Classes
    FileSystemUtilities
  22. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  23. def collectNodesIntoComp(mod: Module): Unit

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    Definition Classes
    Backend
  24. val compIndices: HashMap[String, Int]

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    Definition Classes
    VerilogBackend
  25. def compile(c: Module, flags: Option[String]): Unit

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    Definition Classes
    VerilogBackendBackend
  26. def computeMemPorts(mod: Module): Unit

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    Definition Classes
    Backend
  27. def connectResets: Unit

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    Definition Classes
    Backend
  28. def convertMaskedWrites(mod: Module): Unit

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    Definition Classes
    Backend
  29. def copyToTarget(filename: String): Unit

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    Definition Classes
    FileSystemUtilities
  30. def createOutputFile(name: String): FileWriter

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    Definition Classes
    FileSystemUtilities
  31. def delimitUncommentedPortDecls(portDecls: ArrayBuffer[StringBuilder]): Unit

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    Definition Classes
    VerilogBackend
  32. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

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    Definition Classes
    VerilogBackend
  33. def elaborate(c: Module): Unit

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    Definition Classes
    VerilogBackendBackend
  34. def emitAssert(a: Assert): String

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    Definition Classes
    VerilogBackend
  35. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

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    Definition Classes
    VerilogBackend
  36. def emitDec(node: Node): String

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    Definition Classes
    VerilogBackendBackend
  37. def emitDecBase(node: Node, wire: String = "wire"): String

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    Definition Classes
    VerilogBackend
  38. def emitDecReg(node: Node): String

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    Definition Classes
    VerilogBackend
  39. def emitDecs(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  40. def emitDef(node: Node): String

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    Definition Classes
    VerilogBackendBackend
  41. def emitDef(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  42. def emitDefs(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  43. def emitInit(node: Node): String

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    Definition Classes
    VerilogBackend
  44. def emitInits(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  45. def emitModuleText(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  46. def emitPortDef(m: MemAccess, idx: Int): String

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    Definition Classes
    VerilogBackend
  47. def emitPrintf(p: Printf): String

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    Definition Classes
    VerilogBackend
  48. def emitRef(node: Node): String

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    Definition Classes
    VerilogBackendBackend
  49. def emitRef(c: Module): String

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    Definition Classes
    Backend
  50. def emitReg(node: Node): String

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    Definition Classes
    VerilogBackend
  51. def emitRegs(c: Module): StringBuilder

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    Definition Classes
    VerilogBackend
  52. def emitTmp(node: Node): String

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    Definition Classes
    VerilogBackendBackend
  53. def emitWidth(node: Node): String

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    Definition Classes
    VerilogBackend
  54. val emittedModules: HashSet[String]

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    Definition Classes
    VerilogBackend
  55. def ensureDir(dir: String): String

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    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes
    FileSystemUtilities
  56. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  57. def equals(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  58. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

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    Definition Classes
    Backend
  59. def extractClassName(comp: Module): String

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    Definition Classes
    Backend
  60. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  61. def findCombLoop: Unit

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    Definition Classes
    Backend
  62. def findConsumers(mod: Module): Unit

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    Definition Classes
    Backend
  63. def findGraphDims: (Int, Int, Int)

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    Definition Classes
    Backend
  64. def flattenAll: Unit

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    Definition Classes
    Backend
  65. def flushModules(defs: LinkedHashMap[String, LinkedHashMap[StringBuilder, ArrayBuffer[Module]]], level: Int): Unit

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    Definition Classes
    VerilogBackend
  66. def forceMatchingWidths: Unit

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    Definition Classes
    Backend
  67. def fullyQualifiedName(m: Node): String

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    Definition Classes
    Backend
  68. def gatherClocksAndResets: Unit

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    Definition Classes
    Backend
  69. def genHarness(c: Module, name: String): Unit

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    Definition Classes
    VerilogBackend
  70. def genIndent(x: Int): String

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    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes
    protected
    Definition Classes
    Backend
  71. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any
  72. def hashCode(): Int

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    Definition Classes
    AnyRef → Any
  73. def inferAll(mod: Module): Int

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    Definition Classes
    Backend
  74. def isBitsIo(node: Node, dir: IODirection): Boolean

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    Nodes which are created outside the execution trace from the toplevel component constructor (i.e.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes
    Backend
  75. def isEmittingComponents: Boolean

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    Definition Classes
    VerilogBackendBackend
  76. def isInObject(n: Node): Boolean

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    Definition Classes
    Backend
  77. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any
  78. val keywords: Set[String]

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    Definition Classes
    Backend
  79. def link(dir: String, target: String, objects: Seq[String], isCC: Boolean = false, isLib: Boolean = false): Unit

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    Definition Classes
    FileSystemUtilities
  80. def lowerNodes(mod: Module): Unit

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    Definition Classes
    Backend
  81. def markComponents: Unit

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    Definition Classes
    Backend
  82. val memConfs: HashMap[String, String]

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    Definition Classes
    VerilogBackend
  83. def nameAll(): Unit

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    Definition Classes
    Backend
  84. def nameBindings: Unit

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    Definition Classes
    Backend
  85. def nameRsts: Unit

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    Backend
  86. val nameSpace: HashSet[String]

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    Definition Classes
    Backend
  87. final def ne(arg0: AnyRef): Boolean

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    AnyRef
  88. val needsLowering: Set[String]

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    Definition Classes
    VerilogBackendBackend
  89. final def notify(): Unit

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    AnyRef
  90. final def notifyAll(): Unit

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    Definition Classes
    AnyRef
  91. def printStack: Unit

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    Backend
  92. def pruneUnconnectedIOs: Unit

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    Definition Classes
    Backend
  93. def removeTypeNodes(mod: Module): Int

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    All classes inherited from Data are used to add type information and do not represent logic itself.

    All classes inherited from Data are used to add type information and do not represent logic itself.

    Definition Classes
    Backend
  94. def renameNodes(nodes: Seq[Node], sep: String = "_"): Unit

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    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Ensures each node such that it has a unique name across the whole hierarchy by prefixing its name by a component path (except for "reset" and all nodes in *c*).

    Definition Classes
    Backend
  95. def run(cmd: String): Boolean

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    Definition Classes
    FileSystemUtilities
  96. def sortComponents: Unit

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    Definition Classes
    Backend
  97. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef
  98. def synthesizeable(node: Node): Boolean

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    Definition Classes
    VerilogBackend
  99. def toString(): String

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    Definition Classes
    AnyRef → Any
  100. def topMod: Module

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    Definition Classes
    Backend
  101. val transforms: ArrayBuffer[(Module) ⇒ Unit]

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    Definition Classes
    Backend
  102. def verifyAllMuxes: Unit

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    Definition Classes
    Backend
  103. def verifyComponents: Unit

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    Definition Classes
    Backend
  104. final def wait(): Unit

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    Definition Classes
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    Annotations
    @throws( ... )
  105. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
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    Annotations
    @throws( ... )
  106. final def wait(arg0: Long): Unit

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    Annotations
    @throws( ... )

Inherited from VerilogBackend

Inherited from Backend

Inherited from FileSystemUtilities

Inherited from AnyRef

Inherited from Any

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