Fix

abstract def Factory(exp: Int, width: Int): T

abstract def get_sext(source: Bits): UInt

abstract def toRaw(a: Bits): B

final def !=(arg0: Any): Boolean

def ##[T <: Data](right: T): Fix.this.type

Interface required by Cat is an operator to combine data nodes together

def ##(b: Node): Node

The cat operator to combine two values

0x5 ## 0x3 => 0x53

final def ##(): Int

def +(other: Bundle): Bundle

Create a new Bundle with all the elements of both

def :=(that: Data): Unit

def <>(src: Node): Unit

Connect all elements contained in this to node 'src'

def =/=[T <: Data](right: T): Bool

final def ==(arg0: Any): Boolean

def ===[T <: Data](right: T): Bool

def W0Wtransform(): Unit

Eliminate any zero-width wires attached to this node

def ^^(src: Node): Unit

val _id: Int

The unique id of this node

def _isComplementOf(x: Node): Boolean

def aligned_with(b: T): (B, B, Int)

def apply(name: String): Data

def asDirectionless(): Fix.this.type

set this node as directionless

def asInput(): Fix.this.type

Return this object as an INPUT

final def asInstanceOf[T0]: T0

def asOutput(): Fix.this.type

Sets the direction (*dir*) of instances derived from Bits to OUTPUT or recursively sets members of Bundle/Vec to OUTPUT.

final def asSInt(): SInt

final def asUInt(): UInt

def assign(src: Node): Unit

def calcElements(view: Seq[String]): LinkedHashMap[String, Data]

Populates the cache of elements declared in the Bundle.

def canCSE: Boolean

def checkPort(obj: Any, name: String): Boolean

lazy val chiselName: String

var clock: Option[Clock]

The clock for this node

def clone(): Fix.this.type

def cloneType(): Fix.this.type

def colonEquals(src: Bundle): Unit

def colonEquals[T <: Data](that: Seq[T]): Unit

def colonEquals(that: Bits): Unit

var comp: Option[proc]

def componentOf: Module

Get the module that this node is a part of or the top module if not assigned yet

val consumers: LinkedHashSet[Node]

nodes that consume one of my outputs

def contains(name: String): Boolean

Check if an element exists with that name

def dblLitValue: Double

Convert the node literal to a Double

def do_addsub(b: T, isSub: Boolean = false): T

def do_divide(b: T): T

def do_lesseq(b: T): Bool

def do_lessthan(b: T): Bool

def do_mult(b: T): T

def do_truncate(source: T): Unit

var driveRand: Boolean

lazy val elements: LinkedHashMap[String, Data]

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

Compare two nodes

def equalsForCSE(x: Node): Boolean

val exp: Int

def finalize(): Unit

def flatten: Array[(String, Bits)]

def flip(): Fix.this.type

Change all INPUT to OUTPUT and visa versa for all elements in this Bundle

def floLitValue: Float

Convert the node literal to a Float

def fromBits(b: Bits): Fix.this.type

def fromMap(elemmap: Map[String, Data]): Fix.this.type

Connect all data nodes in the map as inputs for this bundle using the names in the map

def fromNode(n: Node): Fix.this.type

Factory method to create and assign a leaf-type instance out of a subclass of *Node* instance which we have lost the concrete type.

final def getClass(): Class[_]

def getNode: Node

def getWidth(): Int

def hashCode(): Int

def hashCodeForCSE: Int

def illegalAssignment(that: Any): Unit

def infer: Boolean

Called while we're walking the graph inferring the width of nodes.

def init(n: String, w: Int, ins: Node*): Node

Init the node and calculate its width and add inputs to the node

def init(n: String, widthFunc: (⇒ Node) ⇒ Width, ins: Node*): Node

Init the node and calculate its width and add inputs to the node

def initOf(n: String, widthfunc: (⇒ Node) ⇒ Width, ins: Seq[Node]): Node

Init the node and calculate its width and add inputs to the node

val inputs: ArrayBuffer[Node]

The inputs that this node depends on

def isDirectionless: Boolean

check if this node is neither INPUT or OUTPUT

final def isInstanceOf[T0]: Boolean

def isIo: Boolean

def isIo_=(isIo: Boolean): Unit

final def isLit: Boolean

This function determines if a node is a literal, a fixed value

def isTopLevelIO: Boolean

var isTypeNode: Boolean

def isTypeOnly: Boolean

Chisel3 - type-only nodes (no data - no initialization or assignment) This is used to determine which nodes must be Wire() wrapped, and whether Wire() wrapping of the node is legal or not.

def isUsedByClockHi: Boolean

def isWired: Boolean

def isZeroWidth: Boolean

val line: StackTraceElement

The trace information for chisel for this node

def litOf: Literal

def litValue(default: BigInt = BigInt(-1)): BigInt

def maybeFlatten: Seq[Node]

Deprecated: Do not use

var modified: Boolean

var name: String

Name of the instance.

def nameIt(path: String, isNamingIo: Boolean): Unit

Name the bundle, do not use directly, use setName instead

var named: Boolean

named is used to indicate that name was set explicitly and should not be overriden

final def ne(arg0: AnyRef): Boolean

def needWidth(): Int

final def notify(): Unit

final def notifyAll(): Unit

def params: Parameters

def printTree(writer: PrintStream, depth: Int = 4, indent: String = ""): Unit

Prints all members of a node and recursively its inputs up to a certain depth level This method is purely used for debugging

var prune: Boolean

val raw: B

def removeTypeNodes(): Unit

def replaceTree(newNode: Node): Unit

Replace the subtree starting from this node with the indicated replacement

def review(): Unit

Review a node for optimization possibilities if its children have been updated

def setIsTypeNode: Unit

make this node a type node

def setIsWired(value: Boolean): Unit

def setName(n: String): Unit

Set the name of this module to the string 'n'

def setWidth(w: Int): Unit

Force the bit width of a node

final def synchronized[T0](arg0: ⇒ T0): T0

def toBits(): UInt

def toBool(): Bool

Try to convert this data to a Bool

lazy val toNode: Node

def toSInt(): SInt

def toString(): String

def toUInt(): UInt

def usesInClockHi(i: Node): Boolean

val view: Seq[String]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit