DependencyGraph

Instance Constructors

new DependencyGraph(circuit: Circuit, module: Module, blackBoxFactories: Seq[BlackBoxFactory] = Seq.empty)

circuit
the AST being analyzed
module
top level module in the AST, used elsewhere to find top level ports

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def addInstanceName(instanceName: String, moduleName: String): Unit
def addKind(key: String): String
def addMemory(defMemory: DefMemory): Memory
def addPrint(printStatement: Print): Unit
def addSourceInfo(name: String, info: Info): Unit
def addStop(stopStatement: Stop): Unit
def apply(key: String): Option[Expression]
final def asInstanceOf[T0]: T0

Definition Classes
Any
val blackBoxFactories: Seq[BlackBoxFactory]
val circuit: Circuit

the AST being analyzed
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getInfo(name: String): String
def getInfo: String
def getType(key: String): Type
def hasInput(name: String): Boolean
def hasOutput(name: String): Boolean
def hashCode(): Int

Definition Classes
AnyRef → Any
val inlinedPorts: HashSet[String]
val inputPorts: HashSet[String]
val instanceNames: HashMap[String, String]
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
def keys: Iterable[String]
val memories: HashMap[String, Memory]
val memoryKeys: HashMap[String, Memory]
val memoryOutputKeys: HashMap[String, Seq[String]]
val module: Module

top level module in the AST, used elsewhere to find top level ports
val nameToExpression: HashMap[String, Expression]
val nameToType: HashMap[String, Type]
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val nodes: HashSet[String]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
var numberOfMuxes: Int
var numberOfNodes: Int
var numberOfStatements: Int
val outputPorts: HashSet[String]
val prints: ArrayBuffer[Print]
def recordName(key: String): Unit
def recordType(key: String, tpe: Type): Unit
val registerNames: HashSet[String]
val registers: HashMap[String, DefRegister]
val sourceInfo: HashMap[String, String]
val stops: ArrayBuffer[Stop]
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
def update(key: String, e: Expression): Unit
val validNames: HashSet[String]
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
val wires: HashSet[String]

Related Docs: object DependencyGraph | package firrtl_interpreter

class DependencyGraph extends AnyRef

Instance Constructors

new DependencyGraph(circuit: Circuit, module: Module, blackBoxFactories: Seq[BlackBoxFactory] = Seq.empty)

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def addInstanceName(instanceName: String, moduleName: String): Unit

def addKind(key: String): String

def addMemory(defMemory: DefMemory): Memory

def addPrint(printStatement: Print): Unit

def addSourceInfo(name: String, info: Info): Unit

def addStop(stopStatement: Stop): Unit

def apply(key: String): Option[Expression]

final def asInstanceOf[T0]: T0

val blackBoxFactories: Seq[BlackBoxFactory]

val circuit: Circuit

def clone(): AnyRef

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getInfo(name: String): String

def getInfo: String

def getType(key: String): Type

def hasInput(name: String): Boolean

def hasOutput(name: String): Boolean

def hashCode(): Int

val inlinedPorts: HashSet[String]

val inputPorts: HashSet[String]

val instanceNames: HashMap[String, String]

final def isInstanceOf[T0]: Boolean

def keys: Iterable[String]

val memories: HashMap[String, Memory]

val memoryKeys: HashMap[String, Memory]

val memoryOutputKeys: HashMap[String, Seq[String]]

val module: Module

val nameToExpression: HashMap[String, Expression]

val nameToType: HashMap[String, Type]

final def ne(arg0: AnyRef): Boolean

val nodes: HashSet[String]

final def notify(): Unit

final def notifyAll(): Unit

var numberOfMuxes: Int

var numberOfNodes: Int

var numberOfStatements: Int

val outputPorts: HashSet[String]

val prints: ArrayBuffer[Print]

def recordName(key: String): Unit

def recordType(key: String, tpe: Type): Unit

val registerNames: HashSet[String]

val registers: HashMap[String, DefRegister]

val sourceInfo: HashMap[String, String]

val stops: ArrayBuffer[Stop]

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def update(key: String, e: Expression): Unit

val validNames: HashSet[String]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val wires: HashSet[String]

Inherited from AnyRef

Inherited from Any

Ungrouped