Class

firrtl_interpreter.Memory

MemoryPort

Related Doc: package Memory

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abstract class MemoryPort extends AnyRef

Source
Memory.scala
Linear Supertypes
AnyRef, Any
Known Subclasses
ReadPort, ReadWritePort, WritePort
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Inherited
  1. MemoryPort
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Visibility
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Instance Constructors

  1. new MemoryPort()

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Abstract Value Members

  1. abstract def fieldDependencies: Seq[String]

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  2. abstract val latency: Int

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  3. abstract val portName: String

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Concrete Value Members

  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. var address: Int

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  5. final def asInstanceOf[T0]: T0

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  6. var clock: Int

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  7. def clone(): AnyRef

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    Attributes
    protected[java.lang]
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    @throws( ... )

  8. var data: Concrete

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  9. var enable: Boolean

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  10. final def eq(arg0: AnyRef): Boolean

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  11. def equals(arg0: Any): Boolean

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  12. def finalize(): Unit

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    protected[java.lang]
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    @throws( classOf[java.lang.Throwable] )

  13. val fullName: String

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  14. final def getClass(): Class[_]

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  15. def getValue(fieldName: String): Concrete

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  16. def hashCode(): Int

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  17. final def isInstanceOf[T0]: Boolean

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  18. final def ne(arg0: AnyRef): Boolean

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  19. final def notify(): Unit

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  20. final def notifyAll(): Unit

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  21. val outputFieldName: String

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  22. def setValue(fieldName: String, concreteValue: Concrete): Unit

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  23. final def synchronized[T0](arg0: ⇒ T0): T0

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  24. def toString(): String

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  25. final def wait(): Unit

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    @throws( ... )

  26. final def wait(arg0: Long, arg1: Int): Unit

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  27. final def wait(arg0: Long): Unit

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