Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Input Firrtl AST
A transformed Firrtl AST
Convenience method to get annotations relevant to this Transform
Convenience method to get annotations relevant to this Transform
The CircuitState form which to extract annotations
A collection of annotations
The CircuitForm that this transform requires to operate on
The CircuitForm that this transform requires to operate on
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
The CircuitForm that this transform outputs
The CircuitForm that this transform outputs
Perform the transform and update annotations.
Perform the transform and update annotations.
Input Firrtl AST
A transformed Firrtl AST
Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog
This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))
This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes