VerilogRender

Instance Constructors

new VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)

m
the start module
moduleMap
a map of modules so submodules can be discovered
writer
where rendered information is placed.

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def asInstanceOf[T0]: T0

Definition Classes
Any
def assign(e: Expression, value: Expression, info: Info): Unit
val assigns: ArrayBuffer[Seq[Any]]
val at_clock: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
val attachAliases: ArrayBuffer[Seq[Any]]
val attachSynAssigns: ArrayBuffer[Seq[Any]]
def build_netlist(s: Statement): Statement
def build_ports(): Unit
def build_streams(s: Statement): Statement
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
def declare(b: String, n: String, t: Type, info: Info): ArrayBuffer[Seq[Any]]
val declares: ArrayBuffer[Seq[Any]]
def emitVerilogBind(overrideName: String, body: String): DefModule

This emits a verilog module that can be bound to a module defined in chisel.
This emits a verilog module that can be bound to a module defined in chisel. It uses the same machinery as the general emitter in order to insure that parameters signature is exactly the same as the module being bound to
overrideName
Override the module name
body
the body of the bind module
returns
A module constructed from the body
def emit_streams(): Unit
def emit_verilog(): DefModule

The standard verilog emitter, wraps up everything into the verilog
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression, info: Info): ArrayBuffer[Seq[Any]]
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def hashCode(): Int

Definition Classes
AnyRef → Any
def initialize(e: Expression): ArrayBuffer[Seq[Any]]
def initialize_mem(s: DefMemory): Unit
val initials: ArrayBuffer[Seq[Any]]
val instdeclares: ArrayBuffer[Seq[Any]]
def invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val namespace: Namespace
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
val netlist: LinkedHashMap[WrappedExpression, Expression]
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val portdefs: ArrayBuffer[Seq[Any]]
def printf(str: StringLit, args: Seq[Expression]): Seq[Any]
def rand_string(t: Type): Seq[Any]
def regUpdate(r: Expression, clk: Expression): ArrayBuffer[Seq[Any]]
def simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]
val simulates: ArrayBuffer[Seq[Any]]
def stop(ret: Int): Seq[Any]
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
def update(e: Expression, value: Expression, clk: Expression, en: Expression, info: Info): ArrayBuffer[Seq[Any]]
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Doc: package VerilogEmitter

class VerilogRender extends AnyRef

Instance Constructors

new VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

def assign(e: Expression, value: Expression, info: Info): Unit

val assigns: ArrayBuffer[Seq[Any]]

val at_clock: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]

val attachAliases: ArrayBuffer[Seq[Any]]

val attachSynAssigns: ArrayBuffer[Seq[Any]]

def build_netlist(s: Statement): Statement

def build_ports(): Unit

def build_streams(s: Statement): Statement

def clone(): AnyRef

def declare(b: String, n: String, t: Type, info: Info): ArrayBuffer[Seq[Any]]

val declares: ArrayBuffer[Seq[Any]]

def emitVerilogBind(overrideName: String, body: String): DefModule

def emit_streams(): Unit

def emit_verilog(): DefModule

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

def finalize(): Unit

def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression, info: Info): ArrayBuffer[Seq[Any]]

final def getClass(): Class[_]

def hashCode(): Int

def initialize(e: Expression): ArrayBuffer[Seq[Any]]

def initialize_mem(s: DefMemory): Unit

val initials: ArrayBuffer[Seq[Any]]

val instdeclares: ArrayBuffer[Seq[Any]]

def invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]

final def isInstanceOf[T0]: Boolean

val namespace: Namespace

final def ne(arg0: AnyRef): Boolean

val netlist: LinkedHashMap[WrappedExpression, Expression]

final def notify(): Unit

final def notifyAll(): Unit

val portdefs: ArrayBuffer[Seq[Any]]

def printf(str: StringLit, args: Seq[Expression]): Seq[Any]

def rand_string(t: Type): Seq[Any]

def regUpdate(r: Expression, clk: Expression): ArrayBuffer[Seq[Any]]

def simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]

val simulates: ArrayBuffer[Seq[Any]]

def stop(ret: Int): Seq[Any]

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

def update(e: Expression, value: Expression, clk: Expression, en: Expression, info: Info): ArrayBuffer[Seq[Any]]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from AnyRef

Inherited from Any

Ungrouped