class
VerilogRender extends AnyRef
Instance Constructors
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new
VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)
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new
VerilogRender(m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)
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new
VerilogRender(description: Description, portDescriptions: Map[String, Description], m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)
Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: Any): Boolean
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final
def
asInstanceOf[T0]: T0
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val
assigns: ArrayBuffer[Seq[Any]]
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val
asyncInitials: ArrayBuffer[Seq[Any]]
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val
asyncResetAlwaysBlocks: ArrayBuffer[(Expression, Expression, Seq[Any])]
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val
attachAliases: ArrayBuffer[Seq[Any]]
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val
attachSynAssigns: ArrayBuffer[Seq[Any]]
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def
bigIntToVLit(bi: BigInt): String
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def
build_comment(desc: String): Seq[Seq[String]]
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def
build_ports(): Unit
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def
clone(): AnyRef
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def
declare(b: String, n: String, t: Type, info: Info): ArrayBuffer[Seq[Any]]
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def
declare(b: String, n: String, t: Type, info: Info, preset: Expression): ArrayBuffer[Seq[Any]]
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def
declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info, preset: Expression): ArrayBuffer[Seq[Any]]
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def
declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info): ArrayBuffer[Seq[Any]]
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val
declares: ArrayBuffer[Seq[Any]]
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def
emitVerilogBind(overrideName: String, body: String): DefModule
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def
emit_streams(): Unit
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def
emit_verilog(): DefModule
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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val
ifdefDeclares: Map[String, ArrayBuffer[Seq[Any]]]
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val
ifdefInitials: Map[String, ArrayBuffer[Seq[Any]]]
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val
initials: ArrayBuffer[Seq[Any]]
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val
instdeclares: ArrayBuffer[Seq[Any]]
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def
invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]
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final
def
isInstanceOf[T0]: Boolean
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var
maxMemSize: BigInt
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val
noResetAlwaysBlocks: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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val
portdefs: ArrayBuffer[Seq[Any]]
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def
rand_string(t: Type): Seq[Any]
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def
rand_string(t: Type, ifdef: String): Seq[Any]
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def
rand_string(t: Type, ifdefOpt: Option[String]): Seq[Any]
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def
simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]
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val
simulates: ArrayBuffer[Seq[Any]]
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def
stop(ret: Int): Seq[Any]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.