Tail
PrimOps
TailDoPrimGen
ExprGen
TailWidthException
CheckWidths
Target
annotations
TargetDirAnnotation
firrtl
options
TargetSerializer
JsonProtocol
TargetToken
annotations
TestDirectory
BackendCompilationUtilities
TestOptions
util
ToMemIR
memlib
ToProto
proto
ToWorkingIR
passes
TokenTagger
analyses
Top
memlib
TopNameAnnotation
DriverCompatibility
TopWiring
transforms
TopWiringAnnotation
TopWiring
TopWiringOutputFilesAnnotation
TopWiring
TopWiringTransform
TopWiring
Trace
LogLevel
TraceException
ExprGen
TrackTransforms
transforms
Transform
firrtl
TransformBenchmark
hot
TransformClassSerializer
JsonProtocol
TransformDependency
TransformManager
TransformHistoryAnnotation
transforms
TransformLike
options
TransformManager
stage
TransformSerializer
JsonProtocol
Translator
options
TreeCleanUpOrphanException
PropagatePresetAnnotations
TrimIntervals
passes
Type
ir
TypeForeach
Foreachers
TypeMap
Mappers
CInferTypes
InferTypes
TypeSerializer
JsonProtocol
t
MemoizedHash
WrappedType
t1
PrimOps
t2
PrimOps
t3
PrimOps
tab
VerilogEmitter
target
AttributeAnnotation
DescriptionAnnotation
DocStringAnnotation
LoadMemoryAnnotation
MemoryArrayInitAnnotation
MemoryRandomInitAnnotation
MemoryScalarInitAnnotation
PresetAnnotation
SingleTargetAnnotation
GlobalClockAnnotation
InlineAnnotation
ClockListAnnotation
NoDedupMemAnnotation
SinkAnnotation
SourceAnnotation
BlackBoxInlineAnno
BlackBoxPathAnno
BlackBoxResourceAnno
DontTouchAnnotation
FlattenAnnotation
NoDedupAnnotation
OptimizableExtModuleAnnotation
TopWiringAnnotation
targetDir
OneFilePerModule
StageOptions
BlackBoxTargetDirAnno
targetDirName
CommonOptions
ExecutionOptionsManager
targetFile
SingleFile
targetParent
InstanceTarget
IsMember
ModuleTarget
ReferenceTarget
targets
MultiTargetAnnotation
DupedResult
ResolvePaths
DependencyManager
PhaseManager
TransformManager
DedupedResult
DontTouchAnnotation
ManipulateNamesAllowlistAnnotation
ManipulateNamesAllowlistResultAnnotation
ManipulateNamesBlocklistAnnotation
terminate
DoNotTerminateOnExit
testClassName
JQFFuzzOptions
JQFReproOptions
testMethod
JQFFuzzOptions
JQFReproOptions
text
BlackBoxInlineAnno
throwInternalError
Utils
time
Utils
JQFFuzzOptions
timeStamp
BackendCompilationUtilities
times
Utils
toAnnotationSeq
ShellOption
toAnnotations
CommonOptions
FirrtlExecutionOptions
toBitMask
passes
toBits
firrtl
toCircuit
CircuitOption
FirrtlFileAnnotation
FirrtlSourceAnnotation
toDot
RenderDiGraph
toDotRanked
RenderDiGraph
toDotWithLoops
RenderDiGraph
toExp
AnnotationUtils
toGenericTarget
GenericTarget
Target
toInfoMode
InfoModeAnnotation
toMem
DefAnnotatedMemory
toNamed
AnnotationUtils
CircuitTarget
GenericTarget
IsComponent
ModuleTarget
Target
toRenameMap
ManipulateNamesAllowlistResultAnnotation
toSIntType
ConvertFixedToSInt
toSeq
AnnotationSeq
toStr
CheckFlows
toString
Addw
BuildInfo
Dshlw
Add
And
Andr
AsAsyncReset
AsClock
AsFixedPoint
AsInterval
AsSInt
AsUInt
Bits
Cat
Clip
Cvt
DecP
Div
Dshl
Dshr
Eq
Geq
Gt
Head
IncP
Leq
Lt
Mul
Neg
Neq
Not
Or
Orr
Pad
Rem
SetP
Shl
Shr
Squeeze
Sub
Tail
Wrap
Xor
Xorr
Subw
WrappedExpression
WrappedWidth
CompleteTarget
GreaterOrEqual
LesserOrEqual
FileInfo
IntWidth
MultiInfo
NoInfo
MemConf
MemPort
Lineage
Modifications
toSubComponents
AnnotationUtils
toTarget
Utils
CircuitName
CompleteTarget
ComponentName
GenericTarget
ModuleName
Named
toTargetTokens
Target
toTokens
InstanceKey
fromDefInstanceToTargetToken
toWrappedExpression
Utils
to_dir
Utils
to_flip
Utils
to_flow
Utils
tokenize
AnnotationUtils
tokens
CircuitTarget
GenericTarget
IsComponent
ModuleTarget
Target
top
InstanceKeyGraph
Config
topName
CommonOptions
ExecutionOptionsManager
TopNameAnnotation
topWiringDummyOutputFilesFunction
TopWiringTransform
tour
InstanceGraph
tpe
CDefMPort
CDefMemory
EmptyExpression
VRandom
WDefInstanceConnector
WInvalid
WVoid
IRLookup
DefInstance
DefRegister
DefWire
DoPrim
Expression
Field
FixedLiteral
Mux
Port
Reference
SIntLiteral
SubAccess
SubField
SubIndex
UIntLiteral
ValidIf
VectorType
trace
TraceException
Logger
transform
Transform
DependencyManager
IdentityLike
Stage
TransformLike
Translator
AddDefaults
Checks
ConvertLegacyAnnotations
GetIncludes
WriteOutputAnnotations
VerilogMemDelays
RunFirrtlTransformAnnotation
AddCircuit
AddDefaults
AddImplicitEmitter
AddImplicitOutputFile
CatchExceptions
Checks
AddImplicitAnnotationFile
AddImplicitEmitter
AddImplicitFirrtlFile
AddImplicitOutputFile
WriteEmitted
ManipulateNamesAllowlistAnnotation
ManipulateNamesAllowlistResultAnnotation
ManipulateNamesBlocklistAnnotation
ManipulateNamesListAnnotation
AssertSubmoduleAssumptionsAnnotation
Checks
transformNodes
DiGraph
transformOrder
DependencyManager
transformOrderToGraphviz
DependencyManager
transformed
MemDelayAndReadwriteTransformer
transforms
ChirrtlToHighFirrtl
Compiler
HighFirrtlCompiler
HighFirrtlToMiddleFirrtl
IRToWorkingIR
LowFirrtlCompiler
LowFirrtlOptimization
MiddleFirrtlCompiler
MiddleFirrtlToLowFirrtl
MinimumLowFirrtlOptimization
MinimumVerilogCompiler
MinimumVerilogEmitter
NoneCompiler
ResolveAndCheck
SeqTransformBased
VerilogCompiler
VerilogEmitter
annotations
InferReadWrite
ReplSeqMem
stage
firrtl
traversals
firrtl
trigger
Errors
trim
Utils
trueUnderlying
WrappedTransform
tryName
Namespace
tryToComplete
Target
tutorial
root
tval
Mux
type
FIRRTLParser
typeHints
HasSerializationHints