DataRef
passes
DataRefMap
RemoveCHIRRTL
DeadCodeElimination
transforms
Debug
LogLevel
DecInput
wiring
DecKind
wiring
DecOutput
wiring
DecP
PrimOps
DecWire
wiring
DeclarationNotFoundException
Utils
DedupBenchmark
hot
DedupModules
transforms
Deduped
Forms
DedupedResult
transforms
DefAnnotatedMemory
memlib
DefInstance
ir
DefMemory
ir
DefModule
ir
DefModuleSerializer
JsonProtocol
DefNode
ir
DefRegister
ir
DefWire
ir
Default
ir
DefaultEmitterTarget
AddDefaults
Defaults
ExpandWhens
DefnameConflictException
CheckHighFormLike
DefnameDifferentPortsException
CheckHighFormLike
DeletedAnnotation
annotations
DeletedWrapper
phases
Dependency
options
DependencyAPI
options
DependencyAPIMigration
firrtl
DependencyManager
options
DependencyManagerException
options
DependencyManagerUtils
options
Description
firrtl
DescriptionAnnotation
firrtl
DiGraph
graph
DifferingDriverTypesException
InferResets
Direction
ir
DisjointSqueeze
CheckWidths
Div
PrimOps
DivDoPrimGen
ExprGen
DoNotTerminateOnExit
options
DoPrim
ir
DoPrimGen
fuzzer
DocString
firrtl
DocStringAnnotation
firrtl
DontAssertSubmoduleAssumptionsAnnotation
formal
DontCheckCombLoopsAnnotation
transforms
DontTouchAllTargets
transforms
DontTouchAnnotation
transforms
DontTouchNotFoundException
DontTouchAnnotation
DoubleParam
ir
Driver
firrtl
DriverCompatibility
phases
Dshl
PrimOps
DshlDoPrimGen
ExprGen
DshlMaxWidth
CheckWidths
DshlTooBig
CheckWidths
Dshlw
firrtl
Dshr
PrimOps
DshrDoPrimGen
ExprGen
DupMap
DuplicationHelper
DupedResult
transforms
DuplexFlow
firrtl
DuplicateHandling
options
DuplicationHelper
analysis
dataType
DefMemory
DefAnnotatedMemory
debug
Logger
dec2string
Utils
declaration
IRLookup
declare
VerilogRender
SymbolTable
declareInstance
SymbolTable
declareVectorType
VerilogRender
declares
VerilogRender
decls
SplitStatements
decrementDepth
ExprGenParams
dedupInstances
DedupModules
deduplicate
DedupModules
deepReferences
CircuitGraph
defaultConnects
ReplaceMemMacros
defaultFileListName
BlackBoxSourceHelper
defaultGenerators
ExprGenParams
defaultMax
InlineBooleanExpressions
defaultMaxCatLen
CombineCats
defaultMessage
FIRRTLException
defaultPortSeq
MemPortUtils
MemTransformUtils
defname
FIRRTLParser
ExtModule
delete
RenameMap
deleteDirectoryHierarchy
FileUtils
deletedAnnotations
CircuitState
delim
LowerTypes
dependenciesToGraphviz
DependencyManager
dependencyGraph
DependencyManager
dependencyToObject
DependencyManager
dependents
DependencyAPI
CatchExceptions
WrappedTransform
deprecationMessage
CheckScalaVersion
depth
DefMemory
DefAnnotatedMemory
MemConf
description
AttributeAnnotation
DescriptionAnnotation
DocStringAnnotation
deserialize
JsonProtocol
MemoryLoadFileType
Target
deserializeTry
JsonProtocol
diff
Utils
digraph
ConnectionGraph
dir
FIRRTLParser
dirName
TopWiringOutputFilesAnnotation
direction
CDefMPort
Port
directory
TargetDirAnnotation
disableCoverage
JQFFuzzOptions
disableRandomization
RegisterEmissionOption
doNotExitOnHelp
HasParser
dontCheckCombLoops
FirrtlExecutionOptions
dontTouches
DontTouchAllTargets
HasDontTouches
dramaticError
Driver
StageUtils
dramaticUsageError
StageUtils
dramaticWarning
Driver
StageUtils
dummyArg
IsFloor
IsNeg
IsPow
dump
YamlFileWriter
duplicate
LoadMemoryAnnotation
MemoryArrayInitAnnotation
MemoryRandomInitAnnotation
MemoryScalarInitAnnotation
MultiTargetAnnotation
PresetAnnotation
SingleTargetAnnotation
DupedResult
GlobalClockAnnotation
InlineAnnotation
ClockListAnnotation
NoDedupMemAnnotation
SinkAnnotation
SourceAnnotation
BlackBoxInlineAnno
BlackBoxPathAnno
BlackBoxResourceAnno
DedupedResult
DontTouchAnnotation
FlattenAnnotation
ManipulateNamesAllowlistAnnotation
ManipulateNamesAllowlistResultAnnotation
ManipulateNamesBlocklistAnnotation
NoDedupAnnotation
OptimizableExtModuleAnnotation
TopWiringAnnotation
duplicateSubCircuitsFromAnno
Flatten