OfModule
InstanceKey TargetToken fromDefInstanceToTargetToken fromDefModuleToTargetToken fromStringToTargetToken
Old
ReadUnderWrite
OneFilePerModule
firrtl
OpNoMixFix
CheckTypes
OpNotAllSameType
CheckTypes
OpNotAllUInt
CheckTypes
OpNotAnalog
CheckTypes
OpNotCorrectType
CheckTypes
OpNotGround
CheckTypes
OpNotUInt
CheckTypes
Open
ir
OptimizableExtModuleAnnotation
transforms
OptionsException
Driver options
OptionsHelpException
options
OptionsView
options
Or
PrimOps
OrDoPrimGen
ExprGen
Orientation
ir
Orr
PrimOps
OrrDoPrimGen
ExprGen
Output
ir
OutputAnnotationFileAnnotation
options
OutputCaptor
Logger
OutputConfig
firrtl
OutputConfigFileName
memlib
OutputFileAnnotation
stage
o1
PrimOps
o2
PrimOps
o3
PrimOps
ofModule
InstanceTarget
ofModuleTarget
InstanceTarget
oldTargets
ManipulateNamesAllowlistResultAnnotation
onExpr
InlineBitExtractionsTransform InlineCastsTransform LegalizeAndReductionsTransform ReplaceTruncatingArithmetic
onMod
CombineCats InlineBitExtractionsTransform InlineCastsTransform LegalizeAndReductionsTransform LegalizeClocksAndAsyncResetsTransform ReplaceTruncatingArithmetic
onModule
AddDescriptionNodes RemoveAllButClocks SimplifyMems
onStmt
AddDescriptionNodes RemoveAllButClocks CombineCats InlineBitExtractionsTransform InlineCastsTransform LegalizeAndReductionsTransform LegalizeClocksAndAsyncResetsTransform RenameModules ReplaceTruncatingArithmetic
one
Utils
oneOf
GenMonad
op
IsAdd IsMax IsMin IsMul MultiAry DoPrim Verification
op_stream
VerilogEmitter
optAdd
GenericTarget
optimize
ConstantPropagation
optionalPrerequisiteOf
AddDescriptionNodes DependencyAPIMigration Transform VerilogEmitter GetNamespace CleanupNamedTargets EliminateTargetPaths StutteringClockTransform CheckResets DependencyAPI DependencyManager AddDefaults Checks ConvertLegacyAnnotations DeletedWrapper GetIncludes WriteOutputAnnotations CheckChirrtl CheckFlows CheckHighForm CheckTypes CheckWidths CommonSubexpressionElimination InferBinaryPoints InlineInstances Legalize LowerTypes PadWidths RemoveEmpty RemoveValidIf SplitExpressions TrimIntervals VerilogModulusCleanup VerilogPrep ClockListTransform CreateMemoryAnnotations InferReadWrite ReplSeqMem ReplaceMemMacros ResolveMemoryReference VerilogMemDelays WiringTransform FirrtlStage AddCircuit AddDefaults AddImplicitEmitter AddImplicitOutputFile CatchExceptions Checks Compiler AddImplicitAnnotationFile AddImplicitEmitter AddImplicitFirrtlFile AddImplicitOutputFile WriteEmitted WrappedTransform BlackBoxSourceHelper CheckCombLoops CombineCats ConstantPropagation DeadCodeElimination DedupModules FixAddingNegativeLiterals Flatten FlattenRegUpdate GroupComponents InlineBitExtractionsTransform InlineBooleanExpressions InlineCastsTransform LegalizeAndReductionsTransform LegalizeClocksAndAsyncResetsTransform ManipulateNames PropagatePresetAnnotations RemoveReset RemoveWires RenameModules ReplaceTruncatingArithmetic SimplifyMems TopWiringTransform VerilogRename AssertSubmoduleAssumptions ConvertAsserts RemoveVerificationStatements Checks
optionalPrerequisites
AddDescriptionNodes DependencyAPIMigration Transform GetNamespace CleanupNamedTargets EliminateTargetPaths FirrtlToTransitionSystem StutteringClockTransform CheckResets DependencyAPI DependencyManager InlineInstances Legalize PadWidths RemoveEmpty VerilogModulusCleanup VerilogPrep ClockListTransform CreateMemoryAnnotations InferReadWrite ReplSeqMem ReplaceMemMacros ResolveMemoryReference WiringTransform FirrtlStage BlackBoxSourceHelper CheckCombLoops CombineCats ConstantPropagation DeadCodeElimination FixAddingNegativeLiterals Flatten FlattenRegUpdate GroupComponents InlineBitExtractionsTransform InlineBooleanExpressions InlineCastsTransform LegalizeAndReductionsTransform LegalizeClocksAndAsyncResetsTransform ManipulateNames PropagatePresetAnnotations RemoveReset RemoveWires RenameModules ReplaceTruncatingArithmetic SimplifyMems TopWiringTransform VerilogRename AssertSubmoduleAssumptions ConvertAsserts RemoveVerificationStatements
options
EmitAllModulesAnnotation EmitCircuitAnnotation firrtl HasShellOptions InputAnnotationFileAnnotation OutputAnnotationFileAnnotation TargetDirAnnotation WriteDeletedAnnotation InlineInstances ClockListTransform InferReadWrite MemLibOptions ReplSeqMem CompilerAnnotation FirrtlFileAnnotation FirrtlSourceAnnotation InfoModeAnnotation OutputFileAnnotation PrettyNoExprInlining RunFirrtlTransformAnnotation WarnNoScalaVersionDeprecation CheckCombLoops DeadCodeElimination NoCircuitDedupAnnotation AssertSubmoduleAssumptions ClassLogLevelAnnotation LogClassNamesAnnotation LogFileAnnotation LogLevelAnnotation
original
DedupedResult
originalMemoryNameOpt
LoadMemoryAnnotation
originalModule
DupedResult
others
IsAdd IsMax IsMin IsMul
outputAnnotationFileName
FirrtlExecutionOptions
outputBuffer
ConfWriter YamlFileWriter
outputConfig
ClockListAnnotation ReplSeqMemAnnotation
outputDirectory
JQFFuzzOptions
outputFileName
FirrtlOptions
outputFileNameOverride
FirrtlExecutionOptions
outputForm
ChirrtlToHighFirrtl DependencyAPIMigration FirrtlEmitter HighFirrtlToMiddleFirrtl IRToWorkingIR LowFirrtlOptimization MiddleFirrtlToLowFirrtl MinimumLowFirrtlOptimization ResolveAndCheck Transform VerilogEmitter SimpleTransform WrappedTransform IdentityTransform AnalyzeCircuit AnalyzeCircuit
outputFunction
TopWiringOutputFilesAnnotation
outputSuffix
ChirrtlForm CircuitForm EmittedComponent EmittedFirrtlCircuit EmittedFirrtlModule EmittedVerilogCircuit EmittedVerilogModule Emitter FirrtlEmitter FirrtlExecutionOptions HighForm LowForm MidForm SystemVerilogEmitter UnknownForm VerilogEmitter EmittedSMTModelAnnotation GroupAnnotation