This provides a series of transforms that seem to be important to Treadle functionality This was based on firrtl.LowFirrtlOptimization but that has includes passes.memlib.VerilogMemDelays which can cause combinational loops for some firrtl files
There are multiple ways to get a FirrtlCircuit into treadle.
There are multiple ways to get a FirrtlCircuit into treadle. There is a priority to these methods 1. Specify a Firrtl AST with the FirrtlCircuitAnnotation 2. Specify Firrtl text with a FirrtlSourceAnnotation 3. Specify a file containing Firrtl with the FirrtlFileAnnotation
Call a bunch of transforms so TreadleTester can operate
Prepare the AST from low FIRRTL.
Set a default output stuff Sets the default target directory if one has not been defined and uses the circuit name unless there is as TopName override