DeviceTarget

abstract def makeBigIP: BigIP

abstract def topInterface(reset: Reset, accel: AbstractAccelTop): TopInterface

Creates the Top IO and Fringe modules for this target.

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def IO[T <: Data](io: T): T

var SramThreshold: Int

val addrWidth: Int

final def asInstanceOf[T0]: T0

final def bigIP: BigIP

val bufferDepth: Int

val burstSizeBytes: Int

def clone(): AnyRef

val dataWidth: Int

final def eq(arg0: AnyRef): Boolean

def equals(arg0: Any): Boolean

val external_v: Int

val external_w: Int

def finalize(): Unit

var fixadd_latency: Double

var fixdiv_latency: Double

var fixeql_latency: Int

var fixmod_latency: Double

var fixmul_latency: Double

var fixsub_latency: Double

final def getClass(): Class[_]

def hashCode(): Int

final def isInstanceOf[T0]: Boolean

val magPipelineDepth: Int

var makeIO: Function[Data, Data]

val maxBurstsPerCmd: Int

var mux_latency: Int

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

val num_channels: Int

def regFileAddrWidth(n: Int): Int

var sramload_latency: Int

var sramstore_latency: Int

final def synchronized[T0](arg0: ⇒ T0): T0

val target_w: Int

def toString(): String

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val wordsPerStream: Int