Class

fringe.templates.memory

FixOpAccum

Related Doc: package memory

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class FixOpAccum extends Module

Linear Supertypes
LegacyModule, ImplicitModule, UserModule, BaseModule, HasId, InstanceId, AnyRef, Any
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Inherited
  1. FixOpAccum
  2. LegacyModule
  3. ImplicitModule
  4. UserModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new FixOpAccum(tup: (Accum, Int, Double, Double, Boolean, Int, Int, Double))

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  2. new FixOpAccum(t: Accum, numWriters: Int, cycleLatency: Double, opLatency: Double, s: Boolean, d: Int, f: Int, init: Double)

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Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any

  4. def IO[T <: Data](iodef: T): iodef.type

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    Attributes
    protected
    Definition Classes
    BaseModule

  5. def _autoWrapPorts(): Unit

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    Definition Classes
    BaseModule

  6. var _closed: Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule

  7. def _ioPortBound(): Boolean

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    Attributes
    protected
    Definition Classes
    LegacyModule

  8. val accums: Array[(FF, UInt)]

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  9. val activeEn: Bool

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  10. val activeFirst: Bool

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  11. val activeIn1: UInt

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  12. val activeLast: Bool

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  13. val activeReset: Bool

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  14. def annotate(annotation: ChiselAnnotation): Unit

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    Attributes
    protected
    Definition Classes
    BaseModule

  15. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any

  16. val clock: Clock

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    Definition Classes
    ImplicitModule

  17. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  18. val compileOptions: CompileOptions

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    Definition Classes
    UserModule

  19. def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

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  20. def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

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  21. val cw: Int

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  22. val cycleLatency: Double

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  23. val d: Int

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  24. def desiredName: String

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    Definition Classes
    BaseModule

  25. val dispatchLane: UInt

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  26. val drainState: SRFF

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  27. val drain_latency: Int

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  28. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  29. def equals(that: Any): Boolean

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    Definition Classes
    HasId → AnyRef → Any

  30. val f: Int

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  31. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  32. val firstRound: SRFF

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  33. val fixin1: FixedPoint

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  34. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any

  35. def getCommands: Seq[Command]

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    Attributes
    protected
    Definition Classes
    UserModule

  36. def getIds: Seq[HasId]

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    Attributes
    protected
    Definition Classes
    BaseModule

  37. def getModulePorts: Seq[Data]

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    Attributes
    protected
    Definition Classes
    BaseModule

  38. lazy val getPorts: Seq[Port]

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    Definition Classes
    UserModule

  39. def hashCode(): Int

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    Definition Classes
    HasId → AnyRef → Any

  40. val initBits: UInt

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  41. def instanceName: String

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    Definition Classes
    BaseModule → HasId → InstanceId

  42. val io: Bundle { ... /* 6 definitions in type refinement */ }

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    Definition Classes
    FixOpAccum → LegacyModule

  43. val isDrainState: Bool

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  44. val isFirstRound: Bool

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  45. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any

  46. val laneCtr: SingleCounter

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  47. final val name: String

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    Definition Classes
    BaseModule

  48. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

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    Attributes
    protected
    Definition Classes
    LegacyModule → BaseModule

  49. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef

  50. final def notify(): Unit

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    Definition Classes
    AnyRef

  51. final def notifyAll(): Unit

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    Definition Classes
    AnyRef

  52. val numWriters: Int

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  53. val opLatency: Double

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  54. var override_clock: Option[Clock]

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    Attributes
    protected
    Definition Classes
    LegacyModule

  55. var override_reset: Option[Bool]

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    Attributes
    protected
    Definition Classes
    LegacyModule

  56. def parentModName: String

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    Definition Classes
    HasId → InstanceId

  57. def parentPathName: String

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    Definition Classes
    HasId → InstanceId

  58. def pathName: String

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    Definition Classes
    HasId → InstanceId

  59. def portsContains(elem: Data): Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule

  60. def portsSize: Int

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    Attributes
    protected
    Definition Classes
    BaseModule

  61. val reset: Reset

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    Definition Classes
    ImplicitModule

  62. val s: Boolean

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  63. def suggestName(name: ⇒ String): FixOpAccum.this.type

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    Definition Classes
    HasId

  64. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef

  65. val t: Accum

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  66. def toString(): String

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    Definition Classes
    AnyRef → Any

  67. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  68. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  69. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from LegacyModule

Inherited from ImplicitModule

Inherited from UserModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped