NBufMem

Instance Constructors

new NBufMem(tuple: (MemType, List[Int], Int, Int, List[Int], List[Int], NBufXMap, NBufXMap, NBufDMap, NBufDMap, XMap, XMap, BankingMode))
new NBufMem(mem: MemType, logicalDims: List[Int], numBufs: Int, bitWidth: Int, banks: List[Int], strides: List[Int], xBarWMux: NBufXMap, xBarRMux: NBufXMap, directWMux: NBufDMap, directRMux: NBufDMap, broadcastWMux: XMap, broadcastRMux: XMap, bankingMode: BankingMode, inits: Option[List[Double]] = None, syncMem: Boolean = false, fracBits: Int = 0, myName: String = "NBuf")

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: Data](iodef: T): iodef.type

Attributes
protected
Definition Classes
BaseModule
val N: Int
def _autoWrapPorts(): Unit

Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _ioPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
def annotate(annotation: ChiselAnnotation): Unit

Attributes
protected
Definition Classes
BaseModule
final def asInstanceOf[T0]: T0

Definition Classes
Any
val bankingMode: BankingMode
val banks: List[Int]
val banksWidths: List[Int]
val bitWidth: Int
val broadcastRMux: XMap
val broadcastWMux: XMap
val clock: Clock

Definition Classes
ImplicitModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val combinedXBarRMux: XMap
val combinedXBarWMux: XMap
val compileOptions: CompileOptions

Definition Classes
UserModule
def connectBroadcastRPort(rBundle: R_XBar, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]
def connectBroadcastRPort(rBundle: R_XBar, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]
def connectBroadcastWPort(wBundle: W_XBar, muxAddr: (Int, Int)): Unit
def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]
def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]
def connectDirectWPort(wBundle: W_Direct, bufferPort: Int, muxAddr: (Int, Int)): Unit
def connectStageCtrl(done: Bool, en: Bool, port: Int): Unit
def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]
def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]
def connectXBarWPort(wBundle: W_XBar, bufferPort: Int, muxAddr: (Int, Int)): Unit
val ctrl: NBufController
val defaultDirect: List[List[Int]]
val depth: Int
def desiredName: String

Definition Classes
NBufMem → BaseModule
val directRMux: NBufDMap
val directWMux: NBufDMap
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
val flatDirectRMux: DMap
val flatDirectWMux: DMap
val flatXBarRMux: XMap
val flatXBarWMux: XMap
val fracBits: Int
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
UserModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[Data]

Attributes
protected
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
UserModule
val hasBroadcastR: Boolean
val hasBroadcastW: Boolean
val hasDirectR: Boolean
val hasDirectW: Boolean
val hasXBarR: Boolean
val hasXBarW: Boolean
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
val inits: Option[List[Double]]
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
val io: Bundle { ... /* 15 definitions in type refinement */ }

Definition Classes
NBufMem → LegacyModule
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val logicalDims: List[Int]
val mem: MemType
val myName: String
final val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
LegacyModule → BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val numBroadcastR: Int
val numBroadcastRPorts: Int
val numBroadcastW: Int
val numBroadcastWPorts: Int
val numBufs: Int
val numDirectR: Int
val numDirectRPorts: Int
val numDirectW: Int
val numDirectWPorts: Int
val numXBarR: Int
val numXBarRPorts: Int
val numXBarW: Int
val numXBarWPorts: Int
val ofsWidth: Int
var override_clock: Option[Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[Bool]

Attributes
protected
Definition Classes
LegacyModule
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
val portsWithWriter: List[Int]
val reset: Reset

Definition Classes
ImplicitModule
val strides: List[Int]
def suggestName(name: ⇒ String): NBufMem.this.type

Definition Classes
HasId
val syncMem: Boolean
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
val totalOutputs: Int
var usedMuxPorts: List[(String, (Int, Int, Int, Int, Int))]
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
val xBarRMux: NBufXMap
val xBarWMux: NBufXMap

Related Doc: package memory

class NBufMem extends Module

Instance Constructors

new NBufMem(tuple: (MemType, List[Int], Int, Int, List[Int], List[Int], NBufXMap, NBufXMap, NBufDMap, NBufDMap, XMap, XMap, BankingMode))

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): iodef.type

val N: Int

def _autoWrapPorts(): Unit

var _closed: Boolean

def _ioPortBound(): Boolean

def annotate(annotation: ChiselAnnotation): Unit

final def asInstanceOf[T0]: T0

val bankingMode: BankingMode

val banks: List[Int]

val banksWidths: List[Int]

val bitWidth: Int

val broadcastRMux: XMap

val broadcastWMux: XMap

val clock: Clock

def clone(): AnyRef

val combinedXBarRMux: XMap

val combinedXBarWMux: XMap

val compileOptions: CompileOptions

def connectBroadcastRPort(rBundle: R_XBar, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

def connectBroadcastRPort(rBundle: R_XBar, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

def connectBroadcastWPort(wBundle: W_XBar, muxAddr: (Int, Int)): Unit

def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

def connectDirectWPort(wBundle: W_Direct, bufferPort: Int, muxAddr: (Int, Int)): Unit

def connectStageCtrl(done: Bool, en: Bool, port: Int): Unit

def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

def connectXBarWPort(wBundle: W_XBar, bufferPort: Int, muxAddr: (Int, Int)): Unit

val ctrl: NBufController

val defaultDirect: List[List[Int]]

val depth: Int

def desiredName: String

val directRMux: NBufDMap

val directWMux: NBufDMap

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

val flatDirectRMux: DMap

val flatDirectWMux: DMap

val flatXBarRMux: XMap

val flatXBarWMux: XMap

val fracBits: Int

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

val hasBroadcastR: Boolean

val hasBroadcastW: Boolean

val hasDirectR: Boolean

val hasDirectW: Boolean

val hasXBarR: Boolean

val hasXBarW: Boolean

def hashCode(): Int

val inits: Option[List[Double]]

def instanceName: String

val io: Bundle { ... /* 15 definitions in type refinement */ }

final def isInstanceOf[T0]: Boolean

val logicalDims: List[Int]

val mem: MemType

val myName: String

final val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

val numBroadcastR: Int

val numBroadcastRPorts: Int

val numBroadcastW: Int

val numBroadcastWPorts: Int

val numBufs: Int