RegFile

Instance Constructors

new RegFile(w: Int, d: Int, numArgIns: Int = 0, numArgOuts: Int = 0, numArgIOs: Int = 0, argOutLoopbacksMapRaw: Map[Int, Int])

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: Data](iodef: T): iodef.type

Attributes
protected
Definition Classes
BaseModule
def _autoWrapPorts(): Unit

Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _ioPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
val addrWidth: Int
def annotate(annotation: ChiselAnnotation): Unit

Attributes
protected
Definition Classes
BaseModule
val argInRange: List[Int]
def argOut2RegIdx(argOut: Int): Int
val argOutLoopbacksMap: Map[Int, Int]
val argOutLoopbacksMapRaw: Map[Int, Int]
val argOutRange: List[Int]
final def asInstanceOf[T0]: T0

Definition Classes
Any
val clock: Clock

Definition Classes
ImplicitModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compileOptions: CompileOptions

Definition Classes
UserModule
val d: Int
def desiredName: String

Definition Classes
BaseModule
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
UserModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[Data]

Attributes
protected
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
UserModule
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
val io: Bundle { ... /* 9 definitions in type refinement */ }

Definition Classes
RegFile → LegacyModule
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
final val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
LegacyModule → BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
val numArgIOs: Int
val numArgIns: Int
val numArgOuts: Int
var override_clock: Option[Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[Bool]

Attributes
protected
Definition Classes
LegacyModule
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
val pureArgIns: Int
val pureArgOuts: Int
def regIdx2ArgOut(regIdx: Int): Int
val regOuts: Vec[UInt]
val regs: List[FringeFF[UInt]]
val reset: Reset

Definition Classes
ImplicitModule
val rport: MuxN[UInt]
def suggestName(name: ⇒ String): RegFile.this.type

Definition Classes
HasId
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
val w: Int
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Doc: package memory

class RegFile extends Module

Instance Constructors

new RegFile(w: Int, d: Int, numArgIns: Int = 0, numArgOuts: Int = 0, numArgIOs: Int = 0, argOutLoopbacksMapRaw: Map[Int, Int])

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): iodef.type

def _autoWrapPorts(): Unit

var _closed: Boolean

def _ioPortBound(): Boolean

val addrWidth: Int

def annotate(annotation: ChiselAnnotation): Unit

val argInRange: List[Int]

def argOut2RegIdx(argOut: Int): Int

val argOutLoopbacksMap: Map[Int, Int]

val argOutLoopbacksMapRaw: Map[Int, Int]

val argOutRange: List[Int]

final def asInstanceOf[T0]: T0

val clock: Clock

def clone(): AnyRef

val compileOptions: CompileOptions

val d: Int

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

val io: Bundle { ... /* 9 definitions in type refinement */ }

final def isInstanceOf[T0]: Boolean

final val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

val numArgIOs: Int

val numArgIns: Int

val numArgOuts: Int

var override_clock: Option[Clock]

var override_reset: Option[Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

val pureArgIns: Int

val pureArgOuts: Int

def regIdx2ArgOut(regIdx: Int): Int

val regOuts: Vec[UInt]

val regs: List[FringeFF[UInt]]

val reset: Reset

val rport: MuxN[UInt]

def suggestName(name: ⇒ String): RegFile.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

val w: Int

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from LegacyModule

Inherited from ImplicitModule

Inherited from UserModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped