ShiftRegFile

Instance Constructors

new ShiftRegFile(logicalDims: List[Int], bitWidth: Int, banks: List[Int], strides: List[Int], xBarWMux: XMap, xBarRMux: XMap, directWMux: DMap, directRMux: DMap, bankingMode: BankingMode, init: Option[List[Double]], syncMem: Boolean, fracBits: Int, myName: String = "SR")
new ShiftRegFile(tuple: (List[Int], Int, XMap, XMap, DMap, DMap))
new ShiftRegFile(tuple: (List[Int], Int, XMap, XMap, DMap, DMap, Option[List[Double]], Boolean, Int))
new ShiftRegFile(logicalDims: List[Int], bitWidth: Int, xBarWMux: XMap, xBarRMux: XMap, directWMux: DMap, directRMux: DMap, inits: Option[List[Double]], syncMem: Boolean, fracBits: Int, isBuf: Boolean, myName: String)
new ShiftRegFile(p: MemParams)

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: Data](iodef: T): iodef.type

Attributes
protected
Definition Classes
BaseModule
def _autoWrapPorts(): Unit

Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _ioPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
def annotate(annotation: ChiselAnnotation): Unit

Attributes
protected
Definition Classes
BaseModule
final def asInstanceOf[T0]: T0

Definition Classes
Any
val clock: Clock

Definition Classes
ImplicitModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compileOptions: CompileOptions

Definition Classes
UserModule
def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

Definition Classes
MemPrimitive
def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

Definition Classes
MemPrimitive
def connectDirectWPort(wBundle: W_Direct, bufferPort: Int, muxAddr: (Int, Int)): Unit

Definition Classes
MemPrimitive
def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

Definition Classes
MemPrimitive
def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

Definition Classes
MemPrimitive
def connectXBarWPort(wBundle: W_XBar, bufferPort: Int, muxAddr: (Int, Int)): Unit

Definition Classes
MemPrimitive
def decrementAxisCoord(l: List[Int], x: Int): List[Int]
def desiredName: String

Definition Classes
MemPrimitive → BaseModule
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
UserModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[Data]

Attributes
protected
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
UserModule
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
val io: MemInterface

Definition Classes
MemPrimitive → LegacyModule
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
val m: IndexedSeq[(UInt, List[Int], Int, UInt)]
final val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
LegacyModule → BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
var override_clock: Option[Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[Bool]

Attributes
protected
Definition Classes
LegacyModule
val p: MemParams

Definition Classes
MemPrimitive
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
val reset: Reset

Definition Classes
ImplicitModule
def stripCoord(l: HVec[UInt], x: Int): HVec[UInt]
def stripCoord(l: List[Int], x: Int): List[Int]
def suggestName(name: ⇒ String): ShiftRegFile.this.type

Definition Classes
HasId
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
def toString(): String

Definition Classes
AnyRef → Any
var usedMuxPorts: List[(String, (Int, Int, Int, Int))]

Definition Classes
MemPrimitive
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Doc: package memory

class ShiftRegFile extends MemPrimitive

Instance Constructors

new ShiftRegFile(logicalDims: List[Int], bitWidth: Int, banks: List[Int], strides: List[Int], xBarWMux: XMap, xBarRMux: XMap, directWMux: DMap, directRMux: DMap, bankingMode: BankingMode, init: Option[List[Double]], syncMem: Boolean, fracBits: Int, myName: String = "SR")

new ShiftRegFile(tuple: (List[Int], Int, XMap, XMap, DMap, DMap))

new ShiftRegFile(tuple: (List[Int], Int, XMap, XMap, DMap, DMap, Option[List[Double]], Boolean, Int))

new ShiftRegFile(logicalDims: List[Int], bitWidth: Int, xBarWMux: XMap, xBarRMux: XMap, directWMux: DMap, directRMux: DMap, inits: Option[List[Double]], syncMem: Boolean, fracBits: Int, isBuf: Boolean, myName: String)

new ShiftRegFile(p: MemParams)

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): iodef.type

def _autoWrapPorts(): Unit

var _closed: Boolean

def _ioPortBound(): Boolean

def annotate(annotation: ChiselAnnotation): Unit

final def asInstanceOf[T0]: T0

val clock: Clock

def clone(): AnyRef

val compileOptions: CompileOptions

def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

def connectDirectRPort(rBundle: R_Direct, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

def connectDirectWPort(wBundle: W_Direct, bufferPort: Int, muxAddr: (Int, Int)): Unit

def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean, flow: Bool): Seq[UInt]

def connectXBarRPort(rBundle: R_XBar, bufferPort: Int, muxAddr: (Int, Int), castgrps: List[Int], broadcastids: List[Int], ignoreCastInfo: Boolean): Seq[UInt]

def connectXBarWPort(wBundle: W_XBar, bufferPort: Int, muxAddr: (Int, Int)): Unit

def decrementAxisCoord(l: List[Int], x: Int): List[Int]

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

val io: MemInterface

final def isInstanceOf[T0]: Boolean

val m: IndexedSeq[(UInt, List[Int], Int, UInt)]

final val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

var override_clock: Option[Clock]

var override_reset: Option[Bool]

val p: MemParams

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

val reset: Reset

def stripCoord(l: HVec[UInt], x: Int): HVec[UInt]

def stripCoord(l: List[Int], x: Int): List[Int]

def suggestName(name: ⇒ String): ShiftRegFile.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

def toString(): String

var usedMuxPorts: List[(String, (Int, Int, Int, Int))]

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from MemPrimitive

Inherited from LegacyModule

Inherited from ImplicitModule

Inherited from UserModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped