spinal.core

SpinalConfig

Related Docs: object SpinalConfig | package core

case class SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), genVhdlPkg: Boolean = true, mergeAsyncProcess: Boolean = false, asyncResetCombSensitivity: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ...) extends Product with Serializable

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Instance Constructors

  1. new SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), genVhdlPkg: Boolean = true, mergeAsyncProcess: Boolean = false, asyncResetCombSensitivity: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ...)

Value Members

  1. final def !=(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  2. final def ##(): Int

    Definition Classes
    AnyRef → Any

  3. final def ==(arg0: Any): Boolean

    Definition Classes
    AnyRef → Any

  4. def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type

  5. def addTransformationPhase(phase: Phase): SpinalConfig

  6. val anonymSignalPrefix: String

  7. def apply[T <: Component](gen: ⇒ T): SpinalReport[T]

  8. def applyToGlobalData(globalData: GlobalData): Unit

  9. final def asInstanceOf[T0]: T0

    Definition Classes
    Any

  10. val asyncResetCombSensitivity: Boolean

  11. def clone(): AnyRef

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  12. val debug: Boolean

  13. val defaultClockDomainFrequency: IClockDomainFrequency

  14. val defaultConfigForClockDomains: ClockDomainConfig

  15. val device: Device

  16. def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig

  17. val dumpWave: DumpWaveConfig

  18. final def eq(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  19. def finalize(): Unit

    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )

  20. val genVhdlPkg: Boolean

  21. def generate[T <: Component](gen: ⇒ T): SpinalReport[T]

  22. def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]

  23. def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]

  24. final def getClass(): Class[_]

    Definition Classes
    AnyRef → Any

  25. val globalPrefix: String

  26. final def isInstanceOf[T0]: Boolean

    Definition Classes
    Any

  27. val keepAll: Boolean

  28. val memBlackBoxers: ArrayBuffer[Phase]

  29. val mergeAsyncProcess: Boolean

  30. val mode: SpinalMode

  31. final def ne(arg0: AnyRef): Boolean

    Definition Classes
    AnyRef

  32. val netlistFileName: String

  33. final def notify(): Unit

    Definition Classes
    AnyRef

  34. final def notifyAll(): Unit

    Definition Classes
    AnyRef

  35. val oneFilePerComponent: Boolean

  36. val onlyStdLogicVectorAtTopLevelIo: Boolean

  37. val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]

  38. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes
    AnyRef

  39. val targetDirectory: String

  40. val transformationPhases: ArrayBuffer[Phase]

  41. final def wait(): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  42. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

  43. final def wait(arg0: Long): Unit

    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from AnyRef

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