ComponentEmiterVerilog

Value Members

1. final def !=(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

2. final def ##(): Int

   

   Definition Classes

   AnyRef → Any

3. final def ==(arg0: Any): Boolean

   

   Definition Classes

   AnyRef → Any

4. val _referenceSet: LinkedHashSet[String]

   

5. var _referenceSetEnabled: Boolean

   

6. def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String

   

7. def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String

   

8. def accessBoolFixed(e: BitVectorBitAccessFixed): String

   

9. def accessBoolFloating(e: BitVectorBitAccessFloating): String

   

10. val algoIdIncrementalBase: Int

    

    Definition Classes

    ComponentEmiterVerilog → ComponentEmiter

11. var algoIdIncrementalOffset: Int

    

    Definition Classes

    ComponentEmiter

12. def allocateAlgoIncrementale(): Int

    

    Definition Classes

    ComponentEmiter

13. val analogs: ArrayBuffer[BaseType]

    

    Definition Classes

    ComponentEmiter

14. final def asInstanceOf[T0]: T0

    

    Definition Classes

    Any

15. def boolLiteralImpl(e: BoolLiteral): String

    

16. val c: Component

    

17. def clone(): AnyRef

    

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

18. def component: Component

    

    Definition Classes

    ComponentEmiterVerilog → ComponentEmiter

19. val declarations: StringBuilder

    

20. def dispatchExpression(e: Expression): String

    

21. def elaborate(): Unit

    

    Definition Classes

    ComponentEmiter

22. def emitAnalogs(): Unit

    

23. def emitArchitecture(): Unit

    

24. def emitAssignedExpression(that: Expression): String

    

25. def emitAsyncronous(process: AsyncProcess): Unit

    

26. def emitAsyncronousAsAsign(process: AsyncProcess): Boolean

    

27. def emitBaseTypeSignal(baseType: BaseType, name: String): String

    

28. def emitBaseTypeWrap(baseType: BaseType, name: String): String

    

29. def emitBitVectorLiteral(e: BitVectorLiteral): String

    

30. def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit

    

31. def emitEntity(): Unit

    

32. def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String

    

33. def emitEnumPoison(e: EnumPoison): String

    

34. def emitExpression(that: Expression): String

    

35. def emitExpressionNoWrappeForFirstOne(that: Expression): String

    

36. def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int

    

37. def emitMem(mem: Mem[_]): Unit

    

38. def emitMems(mems: ArrayBuffer[Mem[_]]): Unit

    

39. def emitReference(that: DeclarationStatement, sensitive: Boolean): String

    

40. def emitReferenceNoOverrides(that: DeclarationStatement): String

    

41. def emitSignals(): Unit

    

42. def emitSubComponents(openSubIo: HashSet[BaseType]): Unit

    

43. def emitSyncronous(component: Component, group: SyncGroup): Unit

    

44. def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String

    

45. final def eq(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

46. def equals(arg0: Any): Boolean

    

    Definition Classes

    AnyRef → Any

47. val expressionToWrap: LinkedHashSet[Expression]

    

    Definition Classes

    ComponentEmiter

48. def fillExpressionToWrap(): Unit

    

49. def finalize(): Unit

    

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

50. def getBaseTypeSignalInitialisation(signal: BaseType): String

    

51. final def getClass(): Class[_]

    

    Definition Classes

    AnyRef → Any

52. def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y

    

    Definition Classes

    ComponentEmiter

53. def getTrace(): ComponentEmiterTrace

    

54. def hashCode(): Int

    

    Definition Classes

    AnyRef → Any

55. final def isInstanceOf[T0]: Boolean

    

    Definition Classes

    Any

56. def isSubComponentInputBinded(data: BaseType): BaseType

    

    Definition Classes

    ComponentEmiter

57. val logics: StringBuilder

    

58. var memBitsMaskKind: MemBitsMaskKind

    

59. val mems: ArrayBuffer[Mem[_]]

    

    Definition Classes

    ComponentEmiter

60. val mergeAsyncProcess: Boolean

    

    Definition Classes

    ComponentEmiterVerilog → ComponentEmiter

61. final def ne(arg0: AnyRef): Boolean

    

    Definition Classes

    AnyRef

62. final def notify(): Unit

    

    Definition Classes

    AnyRef

63. final def notifyAll(): Unit

    

    Definition Classes

    AnyRef

64. val openSubIo: HashSet[BaseType]

    

    Definition Classes

    ComponentEmiter

65. def operatorImplAsBinaryOperator(verilog: String)(e: BinaryOperator): String

    

66. def operatorImplAsBinaryOperatorLeftSigned(vhd: String)(op: BinaryOperator): String

    

67. def operatorImplAsBinaryOperatorSigned(vhd: String)(op: BinaryOperator): String

    

68. def operatorImplAsCat(e: Cat): String

    

69. def operatorImplAsEnumToEnum(e: CastEnumToEnum): String

    

70. def operatorImplAsMux(e: Multiplexer): String

    

71. def operatorImplAsNoTransformation(func: Cast): String

    

72. def operatorImplAsUnaryOperator(verilog: String)(e: UnaryOperator): String

    

73. def operatorImplResize(func: Resize): String

    

74. def operatorImplResizeSigned(func: Resize): String

    

75. val outputsToBufferize: LinkedHashSet[BaseType]

    

    Definition Classes

    ComponentEmiter

76. val portMaps: ArrayBuffer[String]

    

77. val processes: LinkedHashSet[AsyncProcess]

    

    Definition Classes

    ComponentEmiter

78. def refImpl(e: BaseType): String

    

79. def referehceSetSorted(): LinkedHashSet[String]

    

80. def referenceSetAdd(str: String): Unit

    

81. def referenceSetPause(): Unit

    

82. def referenceSetResume(): Unit

    

83. def referenceSetStart(): Unit

    

84. def referenceSetStop(): Unit

    

85. val referencesOverrides: HashMap[Nameable, Any]

    

    Definition Classes

    ComponentEmiter

86. def result: String

    

87. def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String

    

88. def shiftLeftByIntImpl(e: ShiftLeftByInt): String

    

89. def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String

    

90. def shiftRightByIntImpl(e: ShiftRightByInt): String

    

91. def shiftRightSignedByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String

    

92. val subComponentInputToNotBufferize: HashSet[Any]

    

    Definition Classes

    ComponentEmiter

93. val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]

    

    Definition Classes

    ComponentEmiter

94. final def synchronized[T0](arg0: ⇒ T0): T0

    

    Definition Classes

    AnyRef

95. def toString(): String

    

    Definition Classes

    AnyRef → Any

96. var verilogIndexGenerated: Boolean

    

97. final def wait(): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

98. final def wait(arg0: Long, arg1: Int): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

99. final def wait(arg0: Long): Unit

    

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

100. def wrapSubInput(io: BaseType): Unit

     

     Definition Classes

     ComponentEmiterVerilog → ComponentEmiter

101. val wrappedExpressionToName: HashMap[Expression, String]

     

     Definition Classes

     ComponentEmiter