ASYNC
core
Area
core
Assignable
core
AssignedBits
core
AssignedRange
core
AssignementLevel
VhdlBackend
AssignementNode
core
Attribute
core
AttributeFlag
core
AttributeReady
core
AttributeString
core
abs
SInt
access
Vec
add
AssignedBits AttributeReady BaseType Data
addInOutBinding
Backend
addJsonReport
GlobalData
addNodesIntoComponent
Backend
addPostBackendTask
GlobalData
addReflectionExclusion
Misc
addReservedKeyWordToScope
Backend
addTag
MultiData SpinalTagReady
address
MemWritePayload
addressType
Mem
addressTypeAt
Mem
addressWidth
Mem
algoId
GlobalData
alignLsb
XFix
allocateName
Scope
allocateNames
Backend
allowLiteralToCrossHierarchy
Backend
allowNodesToReadInputOfKindComponent
Backend
allowNodesToReadOutputs
Backend
allowSimplifyIt
BaseType Data
andR
BitVector
apply
AssignedRange B BinaryOperator BitVector BitVectorLiteralFactory BitsLiteral BitsSet BoolLiteral BoolReg Cast Cat ClockDomain Component Encoding EnumCast Function IODirection IntLiteral MaskedLiteral Mem Mux NoneNode RInt Reg RegInit RegNext RegNextWhen Resize S SFix SFix2D Sel SeqMux SpinalEnum SpinalEnumElement SpinalError SpinalExit SpinalInfo SpinalInfoPhase SpinalMap SpinalVhdl SpinalWarning U UFix UFix2D UInt2D UnaryOperator Vec VecBaseType WhenNode cloneOf default default2 ifGen is is2 isPow2 log2Up roundUp signalCache switch switch2 when widthOf wrap
applyComponentIoDefaults
Backend
applyIt
IODirection in inWithNull out outWithNull
asBits
Bits BitsCast Bool Data MultiData SInt SpinalEnumCraft UInt VecBaseType
asBool
BoolCast
asBools
BitVector
asData
Data
asInput
BaseType Data MultiData
asOutput
BaseType Data MultiData
asSInt
Bits Bool SIntCast UInt
asUInt
Bits Bool SInt UIntCast
assignAllByName
Bundle
assignDontCare
BaseType
assignFromAnotherEncoding
SpinalEnumCraft
assignFromBits
Bits Bool Data MultiData SInt SpinalEnumCraft UInt VecBaseType
assignFromImpl
Reg VecAccessAssign
assignMask
UInt
assignSomeByName
Bundle
assignement
CaseNode
autoConnect
XFix
autoResize
Data