Ram_2wrs

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

var _spinalTags: LinkedHashSet[SpinalTag]

def addAttribute(attribute: Attribute): Ram_2wrs.this.type

def addAttribute(name: String, value: Int): Ram_2wrs.this.type

def addAttribute(name: String, value: String): Ram_2wrs.this.type

def addAttribute(name: String): Ram_2wrs.this.type

def addComment(str: String): Component

def addGeneric(name: String, that: Any): Unit

def addGenerics(l: (String, Any)*): Unit

def addPrePopTask(task: () ⇒ Unit): ArrayBuffer[PrePopTask]

Add a new prePopTask

def addRTLPath(path: String): LinkedHashSet[String]

Add the path of the rtl file

def addTag[T <: SpinalTag](spinalTag: T): Ram_2wrs.this.type

def addTags(h: SpinalTag, tail: SpinalTag*): Ram_2wrs.this.type

def addTags[T <: SpinalTag](tags: Iterable[T]): Ram_2wrs.this.type

def afterElaboration(body: ⇒ Unit): ArrayBuffer[PrePopTask]

def asFormalDut(): Ram_2wrs.this.type

final def asInstanceOf[T0]: T0

val children: ArrayBuffer[Component]

Contains an array of all children Component

def clearBlackBox(): Unit

val clockDomain: Handle[ClockDomain]

Get the current clock domain (null if there is no clock domain already set )

def clone(): AnyRef

def component: Component

val definition: $anon forSome {type $anon <: SpinalTagReady { def addComment(str: String): $anon }}

var definitionName: String

Definition Name (name of the entity (VHDL) or module (Verilog))

var definitionNameNoMerge: Boolean

val dslBody: ScopeStatement

final def eq(arg0: AnyRef): Boolean

def equals(obj: Any): Boolean

def existsTag(cond: (SpinalTag) ⇒ Boolean): Boolean

def filterTag(cond: (SpinalTag) ⇒ Boolean): Iterable[SpinalTag]

def findTag(cond: (SpinalTag) ⇒ Boolean): Option[SpinalTag]

def foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit

def foreachTag(body: (SpinalTag) ⇒ Unit): Unit

val genericElements: ArrayBuffer[(String, Any)]

def getAllIo: Set[BaseType]

Get a set of all IO available in the component

final def getClass(): Class[_]

def getDisplayName(): String

def getGeneric: Generic

Return the generic of the blackbox

def getGroupedIO(ioBundleBypass: Boolean): Seq[Data]

def getInstanceCounter: Int

def getMode: Byte

def getName(default: String): String

def getName(): String

def getOrdredNodeIo: List[BaseType]

Sort all IO regarding instanceCounter

def getParentsPath(sep: String = "/"): String

Return the path of the parent

def getPartialName(): String

def getPath(sep: String = "/"): String

Return the path of the component

def getPath(from: Component, to: Component): Seq[Component]

def getRefOwnersChain(): List[Any]

def getRtlPath(separator: String = "/"): String

def getScalaLocationLong: String

def getScalaLocationShort: String

def getScalaTrace(): Throwable

def getTag[T <: SpinalTag](clazz: Class[T]): Option[T]

def getTags(): LinkedHashSet[SpinalTag]

def getTagsOf[T <: SpinalTag]()(implicit tag: ClassTag[T]): Iterable[T]

var globalData: GlobalData

def hasTag[T <: SpinalTag](clazz: Class[T]): Boolean

def hasTag(spinalTag: SpinalTag): Boolean

def hashCode(): Int

var impl: BlackBoxImpl

def instanceAttributes(language: Language): Iterable[Attribute]

def instanceAttributes: Iterable[Attribute]

val io: Bundle { ... /* 2 definitions in type refinement */ }

def isBlackBox: Boolean

def isCompletelyUnnamed: Boolean

def isDefaultGenericValue: Boolean

def isEmptyOfTag: Boolean

var isFormalTester: Boolean

def isInBlackBoxTree: Boolean

final def isInstanceOf[T0]: Boolean

def isLogicLess: Boolean

final def isNamed: Boolean

def isPriorityApplicable(namePriority: Byte): Boolean

var isSpinalSimWb: Boolean

def isUnnamed: Boolean

def isUsingNoNumericType: Boolean

Return true if the blackbox used the tag noNumericType

def isUsingULogic: Boolean

Return true if the blackbox used std_ulogic

val librariesUsages: HashSet[String]

val listRTLPath: LinkedHashSet[String]

var localNamingScope: NamingScope

Name allocation

def makeInputsAnyseq(): Unit

Use anyseq on any input signals to this component which do not have existing assignments.

def mapClockDomain(clockDomain: ClockDomain = ClockDomain.current, clock: Bool = null, reset: Bool = null, enable: Bool = null, resetActiveLevel: Polarity = HIGH, enableActiveLevel: Polarity = HIGH): Unit

Map clock domain signals (clock, reset, enable) to a clockDomain

def mapCurrentClockDomain(clock: Bool, reset: Bool = null, enable: Bool = null, resetActiveLevel: Polarity = HIGH, enableActiveLevel: Polarity = HIGH): Unit

Map clock domains signal to the current ClockDomain

var name: String

var nameableRef: Nameable

final def ne(arg0: AnyRef): Boolean

def noIoPrefix(): Ram_2wrs.this.type

No "io_" prefix in front of the in/out signals

final def notify(): Unit

final def notifyAll(): Unit

def onBody[T](body: ⇒ T): T

def onEachAttributes(doIt: (Attribute) ⇒ Unit): Unit

def overrideLocalName(name: String): Ram_2wrs.this.type

def parent: Component

Get the parent component (null if there is no parent)

var parentScope: ScopeStatement

def parents(of: Component = this, list: List[Component] = Nil): List[Component]

Return a list of all parents of the components

val portA_addressWidth: Int

val portA_clock: ClockDomain

val portA_dataWidth: Int

val portA_duringWrite: DuringWritePolicy

val portA_maskEnable: Boolean

val portA_maskWidth: Int

val portA_readUnderWrite: ReadUnderWritePolicy

val portB_addressWidth: Int

val portB_clock: ClockDomain

val portB_dataWidth: Int

val portB_duringWrite: DuringWritePolicy

val portB_maskEnable: Boolean

val portB_maskWidth: Int

val portB_readUnderWrite: ReadUnderWritePolicy

def postInitCallback(): Ram_2wrs.this.type

def postPopEvent(): Unit

def postPushEvent(): Unit

def prePop(): Unit

def prePopEvent(): Unit

var pulledDataCache: Map[Data, Data]

var refOwner: RefOwnerType

def reflectBaseType(name: String): BaseType

def reflectNames(): Unit

def removeTag(spinalTag: SpinalTag): Ram_2wrs.this.type

def removeTags(tags: Iterable[SpinalTag]): Ram_2wrs.this.type

def replaceStdLogicByStdULogic(): BlackBox

Replace std_logic by std_ulogic

def rework[T](gen: ⇒ T): T

var scalaTrace: Throwable

val scopeProperties: Capture

Rework the component

def setBlackBox(): Unit

def setBlackBoxName(name: String): Ram_2wrs.this.type

Set the name of the blackbox

def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): Ram_2wrs.this.type

def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): Ram_2wrs.this.type

def setCompositeName(nameable: Nameable, postfix: String): Ram_2wrs.this.type

def setCompositeName(nameable: Nameable, namePriority: Byte): Ram_2wrs.this.type

def setCompositeName(nameable: Nameable, weak: Boolean): Ram_2wrs.this.type

def setCompositeName(nameable: Nameable): Ram_2wrs.this.type

def setDefinitionName(name: String, noMerge: Boolean = true): Ram_2wrs.this.type

Set the definition name of the component

def setFormalTester(): Unit

def setInline(impl: BlackBoxImpl): Unit

def setInlineVerilog(str: String): Unit

def setInlineVhdl(str: String): Unit

def setIoCd(cd: ClockDomain = this.clockDomain): Unit

def setLambdaName(isNameBody: ⇒ Boolean)(nameGen: ⇒ String): Ram_2wrs.this.type

def setName(name: String, namePriority: Byte): Ram_2wrs.this.type

def setName(name: String, weak: Boolean): Ram_2wrs.this.type

def setName(name: String): Ram_2wrs.this.type

def setNameAsWeak(): Ram_2wrs.this.type

def setPartialName(name: String, namePriority: Byte, owner: Any): Ram_2wrs.this.type

def setPartialName(name: String, namePriority: Byte): Ram_2wrs.this.type

def setPartialName(name: String, weak: Boolean): Ram_2wrs.this.type

def setPartialName(owner: Nameable, name: String, namePriority: Byte): Ram_2wrs.this.type

def setPartialName(owner: Nameable, name: String, weak: Boolean): Ram_2wrs.this.type

def setPartialName(name: String): Ram_2wrs.this.type

def setPartialName(owner: Nameable, name: String): Ram_2wrs.this.type

def setPartialName(owner: Nameable): Ram_2wrs.this.type

def setRefOwner(that: Any): Unit

def setScalaLocated(source: ScalaLocated): Ram_2wrs.this.type

def setWeakName(name: String): Ram_2wrs.this.type

def spinalSimWhiteBox(): Unit

def spinalTags: LinkedHashSet[SpinalTag]

def stub(): Ram_2wrs.this.type

Empty Component, remove logic in component and assign zero on output port as stub

final def synchronized[T0](arg0: ⇒ T0): T0

val technology: MemTechnologyKind

def toString(): String

def traceDisable(recursive: Boolean = true): Ram_2wrs.this.type

def traceEnable(recursive: Boolean = true): Ram_2wrs.this.type

var traceEnabled: Boolean

def unsetName(): Ram_2wrs.this.type

val userCache: Map[Any, Any]

Used to store arbitrary object related to the component

def valCallback[T](ref: T, name: String): T

def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit

def valCallbackRec(ref: Any, name: String): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def walkComponents(body: (Component) ⇒ Unit): Unit

def withAutoPull(): Unit

var withHierarchyAutoPull: Boolean

def withKeywords(): Unit

var withVitalOutputs: Boolean

def withoutKeywords(): Unit

var withoutReservedKeywords: Boolean

val wordCount: Int

val wordWidth: Int

def finalize(): Unit