core
Sometime, creating a Component to define some logic is overkill.
Sometime, creating a Component to define some logic is overkill.
For this kind of cases you can use Area to define a group of signals/logic.
val tickConter = new Area{ val tick = Reg(UInt(8 bits) init(0) tick := tick + 1 }
Assignable trait
Abstract base class of all Spinal types
Base type Cast
Base type factory
BigDecimal Builder
BigInt Builder
Represent the number of bit of a data
BitVector is a family of types for storing multiple bits of information in a single value.
BitVector is a family of types for storing multiple bits of information in a single value.
This type has three subtypes that can be used to model different behaviors:
BitsUInt (unsigned integer)SInt (signed integer)
Base class to create Bit Vector from literal
The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.
The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.
val myBits1 = Bits(32 bits) val myBits2 = B(25, 8 bits) val myBits3 = B"8'xFF" val myBits4 = B"1001_0011
Bits factory used for instance by the IODirection to create a in/out Bits
Bitwise Operation
Bitwise Operation
the type which is associated with the bitwise operation
A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.
A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.
class Ram_1w_1r(wordWidth: Int, wordCount: Int) extends BlackBox { val generic = new Generic { val wordCount = Ram_1w_1r.this.wordCount val wordWidth = Ram_1w_1r.this.wordWidth } val io = new Bundle { val clk = in Bool() val wr = new Bundle { val en = in Bool() val addr = in UInt (log2Up(wordCount) bit) val data = in Bits (wordWidth bit) } val rd = new Bundle { val en = in Bool() val addr = in UInt (log2Up(wordCount) bit) val data = out Bits (wordWidth bit) } } mapClockDomain(clock=io.clk) }
Create a blackBox with std_ulogic instead of std_logic
The Bool type corresponds to a hardware boolean value (True or False)
The Bool type corresponds to a hardware boolean value (True or False)
val myBool = Bool() myBool := False myBool := Bool(false)
Bundle for the edge detection
Bool factory used for instance by the IODirection to create a in/out Bool()
A Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name.
A Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name.
A Bundle can be used to model data structures, buses and interfaces.
val cmd = new Bundle{ val init = in Bool() val start = in Bool() val result = out Bits(32 bits) }
Clock and reset signals can be combined to create a clock domain.
Clock and reset signals can be combined to create a clock domain.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain. Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally
Clock Area with a special clock enable.
Clock Area with a special clock enable.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.
Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.
Abstract class used to create a new Component
Abstract class used to create a new Component
class MyAndGate extends Component { val io = new Bundle{ val a,b = in Bool() val res = out Bool() } io.res := io.a & io.b }
Cycles number representation
Should not extends AnyVal, Because it create kind of strange call stack move that make error reporting miss accurate
target device
Double Builder
Implicit clause builder for elseWhen
Endianness enumeration
Node representation which contains the value of an SpinalEnumElement
Exponent representation
Create a generic for a BlackBox
Create a generic for a BlackBox
class myMemory(sizeMem: Int) extends BlackBox{ val generic = new Generic{ val size = sizeMem } val io = new Bundle { ... } }
Global data
Get a link to the globalData
Frequency representation
Declare ports
Declare ports
A port is some Data with a direction, which can be in, out or inout.
There are 4 available syntaxes, which are all equivalent:
val braces = in(Vec(Bool, 5)) val short = in Vec (Bool, 5) val spaceful = in port Vec(Bool, 5) val variadic = Vec(Bool, 5) in(variadic)
The "braces" syntax is short and generic, but it uses braces.
The "short" syntax is short, but it is formatted with a space between the type and its parameters, and it can be used only with:
BoolBitsUIntSIntVecThe "spaceful" syntax is generic and beautiful, but more verbose.
The "variadic" syntax can be used with any number of ports, but can be used only if the ports types are already declared.
Create an Area which can be assign to a data
Create an Area which can be assign to a data
class Counter extends ImplicitArea[UInt]{ val cnt = Reg(UInt(8 bits) ... override def implicitValue: UInt = cnt } val myCounter = Counter() io.myUInt = myCounter
Integer Builder
system verilog interface
system verilog interface
case class MyIf(width: Int = 8) extends Interface with IMasterSlave { val wParam = addGeneric("WIDTH", width, default = "8") val a = Bits(width bits) tieGeneric(a, wParam) val b = Bool() val c = SInt(8 bits) override def asMaster = mst @modport def mst = { out(a, b, c) } @modport def slv = { in(a, b, c) } }
Literal builder
Literal builder
S/U/B"[[size']base]value"e.g.:
B"8'xFF"`
Masked Literal
Masked Literal
val itMatch = myBits === M"00--10--" // - don't care value
Min max base function
Base class for multi data like Vec, Bundle
Base operations for numbers
Base operations for numbers
the type which is associated with the base operation
Base class for the Physical representation (Hertz, Time, ...)
Base class for the Physical representation (Hertz, Time, ...)
When formatting (e.g. via f-interpolation) one can use: - precision to specify precsion (e.g. "%.3f" for three digits past comma) - width to pad with space to a specified length (e.g. "%5f" to get at least 5 characters) - left justified padding (e.g. "%-5f" to pad right to 5 characters) - alternate to print w/o unit (e.g. "%#f")
Position representation
Implicit Range helper
Use to give value by reference to a function
ResetArea allow to reset an area with a special reset combining with the current reset (cumulative).
ResetArea allow to reset an area with a special reset combining with the current reset (cumulative).
Signed fix point
Signed fix point
The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.
The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.
val mySInt = SInt(8 bits) mySInt := S(4, 8 bits) + S"0000_1111" mySInt := S(4) - S"h1A"
SInt factory used for instance by the IODirection to create a in/out SInt
Implicit SInt helper
Safe Stack
Slice size representation
Define a clock domain which is x time slower than the current clock.
Define a clock domain which is x time slower than the current clock.
Spinal configuration for the generation of the RTL
Base class for creating enumeration
Base class for creating enumeration
object MyEnum extends SpinalEnum(binarySequential){ val s1, s2, s3, s4 = newElement() }
SpinalEnum contains a list of SpinalEnumElement that is the definition of an element. SpinalEnumCraft is the
hardware representation of the the element.
Hardware representation of an enumeration
Definition of an element of the enumeration
Trait to define an encoding
Spinal report give after the generation of the RTL
Class representing Verilog Struct and VHDL Record data types.
Time representation
Unsigned fix point
Unsigned fix point
Two-dimensional XFix
The UInt type corresponds to a vector of bits that can be used for unsigned integer arithmetic.
The UInt type corresponds to a vector of bits that can be used for unsigned integer arithmetic.
val myUInt = UInt(8 bits) myUInt := U(2,8 bits) myUInt := U(2) myUInt := U"0000_0101" myUInt := U"h1A"
Define an UInt 2D point
Define an UInt 2D point
width of the x point
width of the y point
val positionOnScreen = Reg(UInt2D(log2Up(p.screenResX) bits, log2Up(p.screenResY) bits))
UInt factory used for instance by the IODirection to create a in/out UInt
Implicit UInt helper
A Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name
A Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name
val myVecOfSInt = Vec(SInt(8 bits), 2)
Vec factory
Used by SpinalHDL when/elsewhen/otherwise and WhenBuilder to keep track of the structure.
Base class for SFix and UFix
Set a data to Analog
Used to create a new Bits or cast to Bits
Big-Endian
Create a new Bits of a given width
Create a new Bits of a given width
Create a new Bits
Create a new Bits
Create a new Bool with a value
Create a new Bool with a value
Create a new Bool
Create a new Bool
Concatenate a list of data
Create a new signal, assigned by the given parameter.
Create a new signal, assigned by the given parameter.
Useful to provide a "copy" of something that you can then modify with more conditional assignments.
Implicit Data helper
Implicit senum conversion
Hardware false value
Implicit Int/BigInt/Double to Builder
Implicit conversion from Int/BigInt/String to UInt/SInt/Bits
Little-Endian
SpinalHDL standalone mux with Bool selector
SpinalHDL standalone mux with Bool selector
Types like Enum/Bool/Bits/UInt/SInt can also be used as selector with the method
mux() of their parent BaseType.
Declare a register with a signal type.
Declare a register with a signal type.
val reg1 = Reg(UInt(4 bits))
Declare a register with an initialize value.
Declare a register with an initialize value.
// UInt register of 4 bits initialized with 0 when the reset occurs val reg = RegInit(U"0000")
Register a signal by one clock.
Register a signal by one clock.
val reg1 = Reg(UInt(4 bits)) // Register that updates itself every cycle with a sample of reg1 incremented by 1 val reg2 = RegNext(reg1 + 1)
Register a signal when a condition is true.
Register a signal when a condition is true.
Used to create a new SInt or cast to SInt
Two-dimensional SFix
Create a new SInt of a given width
Create a new SInt of a given width
Create a new SInt
Create a new SInt
Used to create a custom encoding
Used to create a custom encoding
object BR extends SpinalEnum{ val NE, EQ, J, JR = newElement() defaultEncoding = SpinalEnumEncoding("opt")( EQ -> 0, NE -> 1, J -> 2, JR -> 3 ) }
Spinal map
Hardware true value
Used to create a new UInt or cast to UInt
Two-dimensional UFix
Create a new UInt of a given width
Create a new UInt of a given width
Create a new UInt
Create a new UInt
In VHDL add the generic value in the definition of the blackbox
Assertion
Assertion
Binary One hot encoding
Binary One hot encoding
001, 010, 100
Binary Sequential
Binary Sequential
000, 001, 010, 011, 100, 101, ....
Return a new data with the same data structure as the given parameter (including bit width)
default statement of a SpinalHDL switch/ case
default statement of a SpinalHDL switch/ case
Gray encoding (sequentially assigned)
Gray encoding (sequentially assigned)
000, 001, 011, 010, ...
If used in FSM it is not ensured that only gray encoding preserving transitions are done. If that is needed e.g. for CDC reasons, the transitions must be checked manually.
Scala implicit
Declare an input port
Declare an input port
See IODirection for syntax help.
Inferred encoding
Declare an inout port
Declare an inout port
See IODirection for syntax help.
is statement of a SpinalHDL switch/ case
is statement of a SpinalHDL switch/ case
Check if a number is a power of 2
Give number of bit to encode a given number of states
Native encoding
Transform all unsigned/signed into std_logic_vector
Declare an output port
Declare an output port
See IODirection for syntax help.
Round up a BigInt
Simulation package
case/switch SpinalHDL statement
case/switch SpinalHDL statement
switch(x) {
is(value1) {
// execute when x === value1
}
is(value2) {
// execute when x === value2
}
default {
// execute if none of precedent conditions are meet
}
}
Create a Ulogic tag used by Blackbox in order to transform std_logic into std_ulogic
Return a new data with the same data structure as the given parameter (except bit width)
Allow to express SpinalHDL conditional statements based on a Bool expression like an if.
Allow to express SpinalHDL conditional statements based on a Bool expression like an if.
when(cond1) {
myCnt := 0
}elsewhen(cond2) {
myCnt := myCnt + 1
}otherwise {
myCnt := myCnt - 1
}
Return the number of bit of the given data
Use Bool() (with braces) instead
Sel operation
Sel operation
(Since version ???) Use Select instead
(Since version ???) Use HardType instead
Use apply or port instead: 'val b = in(maybeNull)' or 'val rgb = in port maybeNull'
Use apply or port instead: 'val b = out(maybeNull)' or 'val rgb = out port maybeNull'
(Since version ???) Use xxx.toSFix instead
(Since version ???) Use xxx.toUFix instead
(Since version ???) Use HardType instead