Packages

c

spinal.core.internals

ComponentEmitterVerilog

class ComponentEmitterVerilog extends ComponentEmitter

Linear Supertypes
ComponentEmitter, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. ComponentEmitterVerilog
  2. ComponentEmitter
  3. AnyRef
  4. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new ComponentEmitterVerilog(c: Component, systemVerilog: Boolean, verilogBase: VerilogBase, algoIdIncrementalBase: Int, mergeAsyncProcess: Boolean, asyncResetCombSensitivity: Boolean, anonymSignalPrefix: String, nativeRom: Boolean, nativeRomFilePrefix: String, emitedComponentRef: ConcurrentHashMap[Component, Component], emitedRtlSourcesPath: LinkedHashSet[String], pc: PhaseContext, spinalConfig: SpinalConfig)

Type Members

  1. class AsyncProcess extends AnyRef
    Definition Classes
    ComponentEmitter
  2. class SyncGroup extends AnyRef
    Definition Classes
    ComponentEmitter

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val _referenceSet: LinkedHashSet[String]
  5. var _referenceSetEnabled: Boolean
  6. def accessBitVectorFixed(e: BitVectorRangedAccessFixed): String
  7. def accessBitVectorFloating(e: BitVectorRangedAccessFloating): String
  8. def accessBoolFixed(e: BitVectorBitAccessFixed): String
  9. def accessBoolFloating(e: BitVectorBitAccessFloating): String
  10. val algoIdIncrementalBase: Int
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  11. var algoIdIncrementalOffset: Int
    Definition Classes
    ComponentEmitter
  12. def allocateAlgoIncrementale(): Int
    Definition Classes
    ComponentEmitter
  13. val analogs: ArrayBuffer[BaseType]
    Definition Classes
    ComponentEmitter
  14. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  15. def boolLiteralImpl(e: BoolLiteral): String
  16. val c: Component
  17. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  18. def component: Component
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  19. def cutLongExpressions(): Unit
    Definition Classes
    ComponentEmitter
  20. val declarations: StringBuilder
  21. val definitionAttributes: StringBuilder
  22. def dispatchExpression(e: Expression): String
  23. def elaborate(): Unit
    Definition Classes
    ComponentEmitter
  24. def emitAnalogs(): Unit
  25. def emitArchitecture(): Unit
  26. def emitAssignedExpression(that: Expression): String
  27. def emitAsynchronous(process: AsyncProcess): Unit
  28. def emitAsynchronousAsAsign(process: AsyncProcess): Boolean
  29. def emitBaseTypeSignal(baseType: BaseType, name: String): String
  30. def emitBaseTypeWrap(baseType: BaseType, name: String): String
  31. def emitBitVectorLiteral(e: BitVectorLiteral): String
  32. def emitClockedProcess(emitRegsLogic: (String, StringBuilder) ⇒ Unit, emitRegsInitialValue: (String, StringBuilder) ⇒ Unit, b: StringBuilder, clockDomain: ClockDomain, withReset: Boolean): Unit
  33. def emitEntity(): Unit
  34. def emitEnumDebugLogic(): Unit
  35. def emitEnumLiteralWrap(e: EnumLiteral[_ <: SpinalEnum]): String
  36. def emitEnumParams(): Unit
  37. def emitEnumPoison(e: EnumPoison): String
  38. def emitExpression(that: Expression): String
  39. def emitExpressionNoWrappeForFirstOne(that: Expression): String
  40. def emitInitials(): Unit
  41. def emitLeafStatements(statements: ArrayBuffer[LeafStatement], statementIndexInit: Int, scope: ScopeStatement, assignmentKind: String, b: StringBuilder, tab: String): Int
  42. def emitMaskedLiteral(e: MaskedLiteral): String
  43. def emitMem(mem: Mem[_]): Unit
  44. def emitMems(mems: ArrayBuffer[Mem[_]]): Unit
  45. def emitMuxes(): Unit
  46. def emitReference(that: DeclarationStatement, sensitive: Boolean): String
  47. def emitReferenceNoOverrides(that: DeclarationStatement): String
  48. def emitSignals(): Unit
  49. def emitSubComponents(openSubIo: HashSet[BaseType]): Unit
  50. def emitSynchronous(component: Component, group: SyncGroup): Unit
  51. val enumDebugStringList: ArrayBuffer[(SpinalEnumCraft[_ <: SpinalEnum], String, Int)]
  52. def enumEgualsImpl(eguals: Boolean)(e: BinaryOperator with EnumEncoded): String
  53. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  54. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  55. val expressionToWrap: LinkedHashSet[Expression]
    Definition Classes
    ComponentEmitter
  56. def fillExpressionToWrap(): Unit
  57. def getBaseTypeSignalInitialisation(signal: BaseType): String
  58. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  59. def getOrDefault[X, Y](map: ConcurrentHashMap[X, Y], key: X, default: Y): Y
    Definition Classes
    ComponentEmitter
  60. def getTrace(): ComponentEmitterTrace
  61. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  62. def idToBits[T <: SpinalEnum](enum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String
  63. val initials: ArrayBuffer[LeafStatement]
    Definition Classes
    ComponentEmitter
  64. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  65. def isSubComponentInputBinded(data: BaseType): Expression
    Definition Classes
    ComponentEmitter
  66. val localEnums: LinkedHashSet[(SpinalEnum, SpinalEnumEncoding)]
  67. val localparams: StringBuilder
  68. val logics: StringBuilder
  69. var memBitsMaskKind: MemBitsMaskKind
  70. val mems: ArrayBuffer[Mem[_]]
    Definition Classes
    ComponentEmitter
  71. val mergeAsyncProcess: Boolean
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  72. val multiplexersPerSelect: LinkedHashMap[(Expression with WidthProvider, Int), ArrayBuffer[Multiplexer]]
    Definition Classes
    ComponentEmitter
  73. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  74. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  75. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  76. val openSubIo: HashSet[BaseType]
    Definition Classes
    ComponentEmitter
  77. def operatorImplAsBinaryOperator(verilog: String)(e: BinaryOperator): String
  78. def operatorImplAsBinaryOperatorLeftSigned(vhd: String)(op: BinaryOperator): String
  79. def operatorImplAsBinaryOperatorSigned(vhd: String)(op: BinaryOperator): String
  80. def operatorImplAsCat(e: Cat): String
  81. def operatorImplAsEnumToEnum(e: CastEnumToEnum): String
  82. def operatorImplAsMux(e: BinaryMultiplexer): String
  83. def operatorImplAsNoTransformation(func: Cast): String
  84. def operatorImplAsUnaryOperator(verilog: String)(e: UnaryOperator): String
  85. def operatorImplResize(func: Resize): String
  86. def operatorImplResizeSigned(func: Resize): String
  87. val outputsToBufferize: LinkedHashSet[BaseType]
    Definition Classes
    ComponentEmitter
  88. val portMaps: ArrayBuffer[String]
  89. val processes: LinkedHashSet[AsyncProcess]
    Definition Classes
    ComponentEmitter
  90. def readedOutputWrapEnable: Boolean
    Definition Classes
    ComponentEmitter
  91. def refImpl(e: BaseType): String
  92. def referenceSetAdd(str: String): Unit
  93. def referenceSetPause(): Unit
  94. def referenceSetResume(): Unit
  95. def referenceSetSorted(): LinkedHashSet[String]
  96. def referenceSetStart(): Unit
  97. def referenceSetStop(): Unit
  98. val referencesOverrides: HashMap[Nameable, Any]
    Definition Classes
    ComponentEmitter
  99. def result: String
  100. def shiftLeftByIntFixedWidthImpl(e: ShiftLeftByIntFixedWidth): String
  101. def shiftLeftByIntImpl(e: ShiftLeftByInt): String
  102. def shiftLeftByUIntImpl(e: ShiftLeftByUInt): String
  103. def shiftLeftByUIntImplSigned(e: ShiftLeftByUInt): String
  104. def shiftRightByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
  105. def shiftRightByIntImpl(e: ShiftRightByInt): String
  106. def shiftRightSignedByIntFixedWidthImpl(e: ShiftRightByIntFixedWidth): String
  107. val subComponentInputToNotBufferize: HashSet[Any]
    Definition Classes
    ComponentEmitter
  108. val syncGroups: LinkedHashMap[(ClockDomain, ScopeStatement, Boolean), SyncGroup]
    Definition Classes
    ComponentEmitter
  109. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  110. def toString(): String
    Definition Classes
    AnyRef → Any
  111. var verilogIndexGenerated: Boolean
  112. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  113. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  114. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  115. def wrapSubInput(io: BaseType): Unit
    Definition Classes
    ComponentEmitterVerilog → ComponentEmitter
  116. val wrappedExpressionToName: HashMap[Expression, String]
    Definition Classes
    ComponentEmitter

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

Inherited from ComponentEmitter

Inherited from AnyRef

Inherited from Any

Ungrouped