Type Members

1.  trait AllowIoBundle extends AnyRef
2.  trait Area extends NameableByComponent with ContextUser with OwnableRef with ScalaLocated with ValCallbackRec with OverridedEqualsHashCode
3.  trait AssertNodeSeverity extends AnyRef
4.  trait Assignable extends AnyRef

   Assignable trait

5.  trait Attribute extends SpinalTag
6.  class AttributeFlag extends Attribute
7.  class AttributeInteger extends Attribute
8.  sealed trait AttributeKind extends AnyRef
9.  class AttributeString extends Attribute
10.  abstract class BaseType extends Data with DeclarationStatement with StatementDoubleLinkedContainer[BaseType, AssignmentStatement] with Expression

    Abstract base class of all Spinal types

11.  trait BaseTypeCast extends SFixCast with UFixCast

    Base type Cast

12.  trait BaseTypeFactory extends BoolFactory with BitsFactory with UIntFactory with SIntFactory with VecFactory with SFixFactory with UFixFactory

    Base type factory

13.  trait BaseTypePrimitives[T <: BaseType] extends AnyRef
14.  implicit class BigDecimalBuilder extends AnyRef

    BigDecimal Builder

15.  case class BigIntBuilder(i: BigInt) extends Product with Serializable

    BigInt Builder

16.  case class BitCount(value: Int) extends Product with Serializable

    Represent the number of bit of a data

17.  abstract class BitVector extends BaseType with Widthable

    BitVector is a family of types for storing multiple bits of information in a single value.

    BitVector is a family of types for storing multiple bits of information in a single value. This type has three subtypes that can be used to model different behaviours:

    • Bits
    • UInt (unsigned integer)
    • SInt (signed integer)

    See also

    BitVector Documentation

18.  abstract class BitVectorLiteralFactory[T <: BitVector] extends AnyRef

    Base class to create Bit Vector from literal

19.  class Bits extends BitVector with DataPrimitives[Bits] with BaseTypePrimitives[Bits] with BitwiseOp[Bits]

    The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.

    The Bits type corresponds to a vector of bits that does not convey any arithmetic meaning.

    Example:

    1. val myBits1 = Bits(32 bits)
       val myBits2 = B(25, 8 bits)
       val myBits3 = B"8'xFF"
       val myBits4 = B"1001_0011

    See also

    Bits Documentation

20.  trait BitsFactory extends AnyRef

    Bits factory used for instance by the IODirection to create a in/out Bits

21.  trait BitwiseOp[T <: Data] extends AnyRef

    Bitwise Operation

    Bitwise Operation

    T

    the type which is associated with the bitwise operation

22.  abstract class BlackBox extends Component

    A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.

    A blackbox allows the user to integrate an existing VHDL/Verilog component into the design by just specifying the interfaces.

    Example:

    1.  class Ram_1w_1r(wordWidth: Int, wordCount: Int) extends BlackBox {
            val generic = new Generic {
                val wordCount = Ram_1w_1r.this.wordCount
                val wordWidth = Ram_1w_1r.this.wordWidth
            }
            val io = new Bundle {
                val clk = in Bool()
                val wr = new Bundle {
                    val en   = in Bool()
                    val addr = in UInt (log2Up(wordCount) bit)
                    val data = in Bits (wordWidth bit)
                }
                val rd = new Bundle {
                    val en   = in Bool()
                    val addr = in UInt (log2Up(wordCount) bit)
                    val data = out Bits (wordWidth bit)
                }
            }
            mapClockDomain(clock=io.clk)
       }

23.  abstract class BlackBoxULogic extends BlackBox

    Create a blackBox with std_ulogic instead of std_logic

24.  class Bool extends BaseType with DataPrimitives[Bool] with BaseTypePrimitives[Bool] with BitwiseOp[Bool]

    The Bool type corresponds to a boolean value (True or False)

    The Bool type corresponds to a boolean value (True or False)

    Example:

    1. val myBool = Bool()
       myBool := False
       myBool := Bool(false)

    See also

    Bool Documentation

25.  case class BoolEdges() extends Bundle with Product with Serializable

    Bundle for the edge detection

26.  trait BoolFactory extends AnyRef

    Bool factory used for instance by the IODirection to create a in/out Bool()

27.  class Bundle extends MultiData with Nameable with ValCallbackRec
28.  class BundleCase extends Bundle
29.  case class ClockDomain(clock: Bool, reset: Bool = null, dummyArg: DummyTrait = null, softReset: Bool = null, clockEnable: Bool = null, config: ClockDomainConfig = GlobalData.get.commonClockConfig, frequency: ClockFrequency = UnknownFrequency(), clockEnableDivisionRate: DivisionRate = ClockDomain.UnknownDivisionRate()) extends Product with Serializable

    clock and reset signals can be combined to create a clock domain.

    clock and reset signals can be combined to create a clock domain. Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain. Clock domain application work like a stack, which mean, if you are in a given clock domain, you can still apply another clock domain locally

    See also

    ClockDomain Documentation

30.  sealed trait ClockDomainBoolTag extends SpinalTag
31.  case class ClockDomainConfig(clockEdge: EdgeKind = RISING, resetKind: ResetKind = ASYNC, resetActiveLevel: Polarity = HIGH, softResetActiveLevel: Polarity = HIGH, clockEnableActiveLevel: Polarity = HIGH) extends Product with Serializable
32.  case class ClockDomainTag(clockDomain: ClockDomain) extends SpinalTag with Product with Serializable
33.  case class ClockDrivedTag(driver: Bool) extends SpinalTag with Product with Serializable
34.  case class ClockDriverTag(drived: Bool) extends SpinalTag with Product with Serializable
35.  class ClockEnableArea extends Area with PostInitCallback

    Clock Area with a specila clock enable

36.  case class ClockEnableTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
37.  case class ClockSyncTag(a: Bool, b: Bool) extends SpinalTag with Product with Serializable
38.  case class ClockTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
39.  class ClockingArea extends Area with PostInitCallback

    Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.

    Clock domains could be applied to some area of the design and then all synchronous elements instantiated into this area will then implicitly use this clock domain.

    See also

    ClockDomain Documentation

40.  abstract class Component extends NameableByComponent with ContextUser with ScalaLocated with PostInitCallback with Stackable with OwnableRef with SpinalTagReady with OverridedEqualsHashCode with ValCallbackRec

    Abstract class used to create a new Component

    Abstract class used to create a new Component

    Example:

    1. class MyAndGate extends Component {
         val io = new Bundle{
           val a,b = in Bool()
           val res = out Bool()
         }
         io.res := io.a & io.b
       }

    See also

    Component Documentation

41.  class Composite[T <: Nameable] extends Area

    Sometime, creating a Component to define some logic is overkill.

    Sometime, creating a Component to define some logic is overkill. For this kind of cases you can use Area to define a group of signals/logic.

    Example:

    1. val tickConter = new Area{
         val tick = Reg(UInt(8 bits) init(0)
         tick := tick + 1
       }

    See also

    Area Documentation

42.  trait ConditionalContext extends GlobalDataUser
43.  trait ContextUser extends GlobalDataUser with ScalaLocated
44.  case class CyclesCount(value: BigInt) extends Product with Serializable

    Cycles number representation

45.  trait Data extends ContextUser with NameableByComponent with Assignable with SpinalTagReady with GlobalDataUser with ScalaLocated with OwnableRef with OverridedEqualsHashCode with InComponent
46.  class DataPimper[T <: Data] extends DataPrimitives[T]

    Should not extends AnyVal, Because it create kind of strange call stack move that make error reporting miss accurate

47.  trait DataPrimitives[T <: Data] extends AnyRef
48.  trait DataWrapper extends Data
49.  class DefaultTag extends SpinalTag
50.  case class Device(vendor: String = "?", family: String = "?", name: String = "?") extends Product with Serializable

    target device

51.  trait DontName extends Annotation

    Annotations

    @Retention()

52.  case class DoubleBuilder(d: Double) extends Product with Serializable

    Double Builder

53.  trait DummyTrait extends AnyRef
54.  case class DumpWaveConfig(depth: Int = 0, vcdPath: String = "wave.vcd") extends Product with Serializable
55.  sealed trait EdgeKind extends AnyRef
56.  class ElseWhenClause extends AnyRef
57.  implicit class ElseWhenClauseBuilder extends AnyRef

    Implicit clause builder for elseWhen

58.  class EnumLiteral[T <: SpinalEnum] extends Literal with InferableEnumEncodingImpl

    Node representation which contains the value of an SpinalEnumElement

59.  class EnumPoison extends Literal with InferableEnumEncodingImpl
60.  case class ExpNumber(value: Int) extends Product with Serializable

    Exponent representation

61.  class ExternalDriverTag extends SpinalTag
62.  case class FixPointConfig(roundType: RoundType, symmetric: Boolean) extends Product with Serializable
63.  type FixedFrequency = core.ClockDomain.FixedFrequency
64.  class GenerationFlags extends AnyRef
65.  class Generic extends AnyRef

    Create a generic for a BlackBox

    Create a generic for a BlackBox

    Example:

    1. class myMemory(sizeMem: Int) extends BlackBox{
           val generic = new Generic{
            val size = sizeMem
           }
           val io = new Bundle { ... }
       }

66.  case class GenericValue(e: Expression) extends SpinalTag with Product with Serializable
67.  class GlobalData extends AnyRef

    Global data

68.  trait GlobalDataUser extends AnyRef

    Get a link to the globalData

69.  class HardType[T <: Data] extends AnyRef
70.  case class HertzNumber(v: BigDecimal) extends PhysicalNumber[HertzNumber] with Product with Serializable

    Frequency representation

71.  type IClockDomainFrequency = ClockFrequency
72.  trait IODirection extends BaseTypeFactory

    Trait used to set the direction of a data

73.  class IfDefTag extends SpinalTag
74.  abstract class ImplicitArea[T] extends Area

    Create an Area which can be assign to a data

    Create an Area which can be assign to a data

    Example:

    1. class Counter extends ImplicitArea[UInt]{
          val cnt = Reg(UInt(8 bits)
          ...
          override def implicitValue: UInt = cnt
       }
       val myCounter = Counter()
       io.myUInt = myCounter

75.  trait InComponent extends AnyRef
76.  final class IntBuilder extends AnyVal

    Integer Builder

77.  sealed trait Language extends AnyRef
78.  implicit class LiteralBuilder extends AnyRef

    Literal builder S/U/B"e.g. : B"8'xFF"

79.  class MaskedBoolean extends AnyRef

    Masked Literal

    Masked Literal

    Example:

    1. val itMatch = myBits === M"00--10--" // - don't care value

80.  class MaskedLiteral extends AnyRef
81.  class Mem[T <: Data] extends DeclarationStatement with StatementDoubleLinkedContainer[Mem[_], MemPortStatement] with WidthProvider with SpinalTagReady with InComponent
82.  trait MemBlackboxingPolicy extends AnyRef
83.  trait MemPortStatement extends LeafStatement with StatementDoubleLinkedContainerElement[Mem[_], MemPortStatement]
84.  class MemReadAsync extends MemPortStatement with WidthProvider with SpinalTagReady with ContextUser with Expression
85.  class MemReadSync extends MemPortStatement with WidthProvider with SpinalTagReady with ContextUser with Expression
86.  class MemReadWrite extends MemPortStatement with WidthProvider with SpinalTagReady with ContextUser with Expression
87.  case class MemSymbolesMapping(name: String, range: Range) extends Product with Serializable
88.  case class MemSymbolesTag(mapping: Seq[MemSymbolesMapping]) extends SpinalTag with Product with Serializable
89.  trait MemTechnologyKind extends AnyRef
90.  class MemWrite extends MemPortStatement with WidthProvider with SpinalTagReady
91.  class MemWritePayload[T <: Data] extends Bundle
92.  trait MinMaxProvider extends AnyRef

    Min max base function

93.  abstract class MultiData extends Data

    Base class for multi data like Vec, Bundle

94.  trait Nameable extends OwnableRef with ContextUser
95.  trait NameableByComponent extends Nameable with GlobalDataUser
96.  class NamingScope extends AnyRef
97.  trait Num[T <: Data] extends AnyRef

    Base operations for numbers

    Base operations for numbers

    T

    the type which is associated with the base operation

98.  trait OverridedEqualsHashCode extends AnyRef
99.  trait OwnableRef extends AnyRef
100.  abstract class PhysicalNumber[T <: PhysicalNumber[_]] extends AnyRef

     Base class for the Physical representation (Hertz, Time, ...)

101.  sealed trait Polarity extends AnyRef
102.  case class PosCount(value: Int) extends Product with Serializable

     Position representation

103.  case class QFormat(width: Int, fraction: Int, signed: Boolean) extends Product with Serializable
104.  class Ram_1w_1ra extends BlackBox

     Ram 1w 1ra

105.  class Ram_1w_1rs extends BlackBox

     Ram 1w 1rs

106.  class Ram_1wors extends BlackBox

     Ram 1wors

107.  class Ram_1wrs extends BlackBox

     Ram 1wrs

108.  class Ram_2c_1w_1rs extends BlackBox

     Ram 2c 1w 1rs

109.  class Ram_2wrs extends BlackBox

     Ram 2wrs

110.  implicit class RangePimper extends AnyRef

     Implicit Range helper

111.  trait ReadUnderWritePolicy extends AnyRef
112.  case class Ref[T](value: T) extends Product with Serializable

     Use to give value by reference to a function

113.  class ResetArea extends Area with PostInitCallback

     ResetArea allow to reset an area with a special reset combining with the current reset (cumulative)

114.  sealed trait ResetKind extends AnyRef
115.  case class ResetTag(clockDomain: ClockDomain) extends ClockDomainBoolTag with Product with Serializable
116.  sealed trait RoundType extends AnyRef
117.  class SFix extends XFix[SFix, SInt]

     Signed fix point

     Signed fix point

     See also

     SFix Documentation

118.  class SFix2D extends Bundle
119.  trait SFixCast extends AnyRef
120.  trait SFixFactory extends TypeFactory
121.  class SInt extends BitVector with Num[SInt] with MinMaxProvider with DataPrimitives[SInt] with BaseTypePrimitives[SInt] with BitwiseOp[SInt]

     The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.

     The SInt type corresponds to a vector of bits that can be used for signed integer arithmetic.

     Example:

     1. val mySInt = SInt(8 bits)
        mySInt    := S(4, 8 bits) + S"0000_1111"
        mySInt    := S(4) - S"h1A"

     See also

     SInt Documentation

122.  trait SIntFactory extends AnyRef

     SInt factory used for instance by the IODirection to create a in/out SInt

123.  implicit class SIntPimper extends AnyRef

     Implicit SInt helper

124.  class SafeStack[T] extends AnyRef

     Safe Stack

125.  class SafeStackWithStackable[T <: Stackable] extends SafeStack[T]
126.  trait ScalaLocated extends GlobalDataUser
127.  trait ScopeProperty[T] extends AnyRef
128.  class ScopePropertyValue extends AnyRef
129.  case class SlicesCount(value: Int) extends Product with Serializable

     Slice size representation

130.  class SlowArea extends ClockingArea

     Define a clock domain which is x time slower than the current clock

131.  case class SpinalConfig(mode: SpinalMode = null, flags: HashSet[Any] = mutable.HashSet[Any](), debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", privateNamespace: Boolean = false, formalAsserts: Boolean = false, anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = false, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, noRandBoot: Boolean = false, randBootFixValue: Boolean = true, noAssert: Boolean = false, fixToWithWrap: Boolean = true, headerWithDate: Boolean = false, headerWithRepoHash: Boolean = true, removePruned: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) => Unit] = ArrayBuffer[(ArrayBuffer[Phase]) => Unit](), transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ArrayBuffer[Phase] (/*new PhaseMemBlackBoxerDefault(blackboxNothing)*/), rtlHeader: String = null, scopeProperties: LinkedHashMap[ScopeProperty[_], Any] = mutable.LinkedHashMap[ScopeProperty[_], Any](), _withEnumString: Boolean = true) extends Product with Serializable

     Spinal configuration for the generation of the RTL

132.  class SpinalEnum extends Nameable with ScalaLocated

     Base class for creating enumeration

     Base class for creating enumeration

     Example:

     1. object MyEnum extends SpinalEnum(binarySequential){
          val s1, s2, s3, s4 = newElement()
        }

        SpinalEnum contains a list of SpinalEnumElement that is the definition of an element. SpinalEnumCraft is the hardware representation of the the element.

     See also

     Enumeration Documentation

133.  class SpinalEnumCraft[T <: SpinalEnum] extends BaseType with InferableEnumEncodingImpl with BaseTypePrimitives[SpinalEnumCraft[T]] with DataPrimitives[SpinalEnumCraft[T]]

     Hardware representation of an enumeration

134.  class SpinalEnumElement[T <: SpinalEnum] extends Nameable

     Definition of an element of the enumeration

135.  trait SpinalEnumEncoding extends Nameable with ScalaLocated

     Trait to define an encoding

136.  class SpinalExit extends Exception
137.  trait SpinalMode extends AnyRef
138.  class SpinalReport[T <: Component] extends AnyRef

     Spinal report give after the generation of the RTL

139.  abstract class SpinalStruct extends BaseType with Nameable with ValCallbackRec with DataPrimitives[SpinalStruct] with Suffixable

     Class representing Verilog Struct and VHDL Record data types.

140.  trait SpinalTag extends AnyRef
141.  trait SpinalTagReady extends AnyRef
142.  trait Stackable extends AnyRef
143.  class SwitchContext extends AnyRef
144.  case class TimeNumber(v: BigDecimal) extends PhysicalNumber[TimeNumber] with Product with Serializable

     Time representation

145.  implicit class Tuple10Pimper extends TuplePimperBase
146.  implicit class Tuple11Pimper extends TuplePimperBase
147.  implicit class Tuple2Pimper extends TuplePimperBase
148.  implicit class Tuple3Pimper extends TuplePimperBase
149.  implicit class Tuple4Pimper extends TuplePimperBase
150.  implicit class Tuple5Pimper extends TuplePimperBase
151.  implicit class Tuple6Pimper extends TuplePimperBase
152.  implicit class Tuple7Pimper extends TuplePimperBase
153.  implicit class Tuple8Pimper extends TuplePimperBase
154.  implicit class Tuple9Pimper extends TuplePimperBase
155.  class TuplePimperBase extends AnyRef
156.  trait TypeFactory extends AnyRef
157.  class UFix extends XFix[UFix, UInt]

     Unsigned fix point

     Unsigned fix point

     See also

     UFix Documentation

158.  class UFix2D extends Bundle

     Two-dimensional XFix

159.  trait UFixCast extends AnyRef
160.  trait UFixFactory extends TypeFactory
161.  class UInt extends BitVector with Num[UInt] with MinMaxProvider with DataPrimitives[UInt] with BaseTypePrimitives[UInt] with BitwiseOp[UInt]

     The UInt type corresponds to a vector of bits that can be used for unsigned integer arithmetic.

     The UInt type corresponds to a vector of bits that can be used for unsigned integer arithmetic.

     Example:

     1. val myUInt = UInt(8 bits)
         myUInt := U(2,8 bits)
         myUInt := U(2)
         myUInt := U"0000_0101"
         myUInt := U"h1A"

     See also

     UInt Documentation

162.  case class UInt2D(xBitCount: BitCount, yBitCount: BitCount) extends Bundle with Product with Serializable

     Define an UInt 2D point

     Define an UInt 2D point

     xBitCount

     width of the x point

     yBitCount

     width of the y point

     Example:

     1. val positionOnScreen = Reg(UInt2D(log2Up(p.screenResX) bits, log2Up(p.screenResY) bits))

163.  trait UIntFactory extends AnyRef

     UInt factory used for instance by the IODirection to create a in/out UInt

164.  implicit class UIntPimper extends AnyRef

     Implicit UInt helper

165.  type UnknownFrequency = core.ClockDomain.UnknownFrequency
166.  trait ValCallbackRec extends ValCallback

     The Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name.

     The Bundle is a composite type that defines a group of named signals (of any SpinalHDL basic type) under a single name. The Bundle can be used to model data structures, buses and interfaces.

     Example:

     1. val cmd = new Bundle{
          val init   = in Bool()
          val start  = in Bool()
          val result = out Bits(32 bits)
        }

     See also

     Bundle Documentation

167.  class VarAssignementTag extends SpinalTag
168.  class Vec[T <: Data] extends MultiData with IndexedSeq[T]

     The Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name

     The Vec is a composite type that defines a group of indexed signals (of any SpinalHDL basic type) under a single name

     Example:

     1. val myVecOfSInt = Vec(SInt(8 bits), 2)

     See also

     Vec Documentation

169.  class VecAccessAssign[T <: Data] extends Assignable
170.  trait VecFactory extends AnyRef

     Vec factory

171.  class VecBuilder extends AnyRef

     Definition Classes

     VecFactory

172.  class WhenContext extends ConditionalContext with ScalaLocated

     else / else if statement

     else / else if statement

     See also

     when Documentation

173.  abstract class XFix[T <: XFix[T, R], R <: BitVector with Num[R]] extends MultiData

     Base class for SFix and UFix

174.  type dontName = spinal.core.DontName @scala.annotation.meta.field