Packages

trait VerilogBase extends VhdlVerilogBase

Linear Supertypes
VhdlVerilogBase, AnyRef, Any
Known Subclasses
PhaseVerilog
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Inherited
  1. VerilogBase
  2. VhdlVerilogBase
  3. AnyRef
  4. Any
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Visibility
  1. Public
  2. Protected

Value Members

  1. def emitClockEdge(clock: String, edgeKind: EdgeKind): String
  2. def emitCommentAttributes(attributes: Iterable[Attribute]): String
  3. def emitCommentEarlyAttributes(attributes: Iterable[Attribute]): String
  4. def emitDirection(baseType: BaseType): String
  5. def emitEnumLiteral[T <: SpinalEnum](senum: SpinalEnumElement[T], encoding: SpinalEnumEncoding, prefix: String = "`"): String
  6. def emitEnumType(senum: SpinalEnum, encoding: SpinalEnumEncoding, prefix: String = "`"): String
  7. def emitEnumType[T <: SpinalEnum](senum: SpinalEnumCraft[T], prefix: String): String
  8. def emitExpressionWrap(e: Expression, name: String, nature: String): String
  9. def emitExpressionWrap(e: Expression, name: String): String
  10. def emitRange(node: WidthProvider): String
  11. def emitResetEdge(reset: String, polarity: Polarity): String
  12. def emitStructType(struct: SpinalStruct): String
  13. def emitSyntaxAttributes(attributes: Iterable[Attribute]): String
  14. def emitType(e: Expression): String
  15. def expressionAlign(net: String, section: String, name: String): String
  16. def getReEncodingFuntion(spinalEnum: SpinalEnum, source: SpinalEnumEncoding, target: SpinalEnumEncoding): String
  17. val globalPrefix: String
  18. def signalNeedProcess(baseType: BaseType): Boolean
  19. val theme: Tab2