I2C interface definition
Counter of bit write/read.
Filter the SCL and SDA input signals
Define the command interface
Definition of the component I2C Master HAL
Runtime configuartion of the I2C master
Global configuration of the I2C Master
Global configuration of the I2C Master
: Width of the data send
: Number of sampler to generate a bit
: Width of the clockDivider value
: Width of the clockDivider value
Define the response interface
Define the interface of the I2C Master HAL
Definition of the component I2C Slave HAL
Define the command interface
Run-time configuration for the I2CSlave
Generics for the I2C Slave
Generics for the I2C Slave
: Width of the data send/read
: deepth smapling
: Width of the clock divider
Define the response interface
Interface I2C Slave HAL
Detect the rising and falling Edge of the SCL signals
Modes used to manage the master
4 different modes are available for a response ACK : ACK received after writting NACK : NACK recieved after writting DATA : Data read on the bus COLLISION : Collision detected during a write
Mode used to manage the slave
DATA : Send a data to the master NONE : None operation / NACK / Read data from the master ACK : ACK (FREEZE) is done with the response stream.
Counter of bit write/read. MSB is send first on the I2C bus so the counter goes from dataWdith-1 to 0