AxiMemorySim

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

final def asInstanceOf[T0]: T0

val axi: Axi4

val busWordWidth: Int

Bus word width in bytes

val clockDomain: ClockDomain

def clone(): AnyRef

val config: AxiMemorySimConfig

final def eq(arg0: AnyRef): Boolean

final def getClass(): Class[_]

def handleAr(ar: Stream[Axi4Ar]): Unit

def handleAw(aw: Stream[Axi4Aw]): Unit

def handleAwAndW(w: Stream[Axi4W], aw: Stream[Axi4Aw], b: Stream[Axi4B]): Unit

Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform.

def handleR(r: Stream[Axi4R]): Unit

def handleW(w: Stream[Axi4W], b: Stream[Axi4B]): Unit

final def isInstanceOf[T0]: Boolean

val memory: SparseMemory

final def ne(arg0: AnyRef): Boolean

def newAxiJob(address: Long, burstLength: Int): AxiJob

final def notify(): Unit

final def notifyAll(): Unit

val pending_reads: Queue[AxiJob]

val pending_writes: Queue[AxiJob]

def reset(): Unit

def start(): Unit

def stop(): Unit

final def synchronized[T0](arg0: ⇒ T0): T0

val threads: Queue[SimThread]

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

final def wait(): Unit

def finalize(): Unit