trait BusSlaveFactory extends Area
Bus slave factory is a tool that provide an abstract and smooth way to define register bank
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abstract
type
RefOwnerType
- Definition Classes
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Abstract Value Members
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abstract
def
busDataWidth: Int
Return the data width of the bus
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abstract
def
nonStopWrite[T <: Data](that: T, bitOffset: Int = 0, documentation: String = null): T
Permanently assign that by the bus write data from bitOffset
- abstract def onReadPrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
- abstract def onWritePrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: ⇒ Unit): Unit
- abstract def readAddress(): UInt
- abstract def readHalt(): Unit
- abstract def readPrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
- abstract def writeAddress(): UInt
- abstract def writeHalt(): Unit
- abstract def writePrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
Concrete Value Members
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final
def
!=(arg0: Any): Boolean
- Definition Classes
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final
def
##(): Int
- Definition Classes
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final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
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val
_config: BusSlaveFactoryConfig
Configuration of the BusSlaveFactory
Configuration of the BusSlaveFactory
- Attributes
- protected
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final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
- def clearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
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def
clone(): AnyRef
- Attributes
- protected[java.lang]
- Definition Classes
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- @native() @throws( ... )
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def
component: Component
- Definition Classes
- ContextUser
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def
createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): Flow[T]
Create a writable Flow register of type dataType at address and placed at bitOffset in the word
- def createReadAndClearOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
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def
createReadAndWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a read write register of type dataType at address and placed at bitOffset in the word
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def
createReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words read register of type dataType
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def
createReadOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a read only register of type dataType at address and placed at bitOffset in the word
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def
createWriteAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words write and read register of type dataType
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def
createWriteMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words write register of type dataType
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def
createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a write only register of type dataType at address and placed at bitOffset in the word
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def
doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit
Instanciate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.
Instanciate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared. This register is readable at address and placed at bitOffset in the word
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def
drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Drive that with a register writable at address placed at bitOffset in the word
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def
driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Drive that with a register writable and readable at address placed at bitOffset in the word
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def
driveAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Drive and read that on multi-word
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def
driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0): Unit
Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word
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def
driveMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Drive that on multi-words
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final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
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def
equals(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
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def
finalize(): Unit
- Attributes
- protected[java.lang]
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- @throws( classOf[java.lang.Throwable] )
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def
foreachReflectableNameables(doThat: (Any) ⇒ Unit): Unit
- Definition Classes
- Nameable
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final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
- def getConfig: BusSlaveFactoryConfig
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def
getDisplayName(): String
- Definition Classes
- Nameable
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def
getInstanceCounter: Int
- Definition Classes
- ContextUser
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def
getName(default: String): String
- Definition Classes
- Nameable
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def
getName(): String
- Definition Classes
- Nameable
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def
getRefOwnersChain(): List[Any]
- Definition Classes
- OwnableRef
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def
getScalaLocationLong: String
- Definition Classes
- ScalaLocated
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def
getScalaLocationShort: String
- Definition Classes
- ScalaLocated
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def
getScalaTrace(): Throwable
- Definition Classes
- ScalaLocated
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val
globalData: GlobalData
- Definition Classes
- GlobalDataUser
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def
hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
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final
def
isInstanceOf[T0]: Boolean
- Definition Classes
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def
isNamed: Boolean
- Definition Classes
- Nameable
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def
isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
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def
isReading(address: BigInt): Bool
Return true if the bus is reading
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def
isUnnamed: Boolean
- Definition Classes
- Nameable
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def
isWriting(address: BigInt): Bool
Return true if the bus is writing
- def multiCycleRead(address: AddressMapping, cycles: BigInt): Unit
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final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
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final
def
notify(): Unit
- Definition Classes
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- Annotations
- @native()
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final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
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def
onRead(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit
Call doThat when a read transaction occurs on address
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def
onWrite(address: BigInt, documentation: String = null)(doThat: ⇒ Unit): Unit
Call doThat when a write transaction occurs on address
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val
parentScope: ScopeStatement
- Definition Classes
- ContextUser
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def
read[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
When the bus read the address, fill the response with that at bitOffset
- def readAddress(address: AddressMapping): UInt
- def readAndClearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
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def
readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0, documentation: String = null): Unit
Make that readable and writable at address and placed at bitOffset in the word
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def
readAndWriteMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to write/read that from address
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def
readMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to read that from address If that is bigger than one word it extends the register on followings addresses
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def
readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int): Unit
Read that and consume the transaction when a read happen at address.
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def
readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt): Unit
Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.
Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.
- Note
in order to avoid to read wrong data read first the address which contains the valid signal. Little : payload - valid at address 0x00 Big : valid - payload at address 0x00 Once the valid signal is true you can read all registers
- def readSyncMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]
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val
refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @dontName()
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def
reflectNames(): Unit
- Definition Classes
- Area
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def
setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setCompositeName(nameable: Nameable, postfix: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setCompositeName(nameable: Nameable, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setCompositeName(nameable: Nameable, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setCompositeName(nameable: Nameable): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setConfig(value: BusSlaveFactoryConfig): BusSlaveFactory.this.type
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def
setName(name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setName(name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(owner: Nameable, name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(owner: Nameable, name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setPartialName(owner: Nameable, name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
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def
setScalaLocated(source: ScalaLocated): BusSlaveFactory.this.type
- Definition Classes
- ScalaLocated
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def
setWeakName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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def
setWordEndianness(value: Endianness): BusSlaveFactory
Set the endianness during write/read multiword
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final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
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def
toString(): String
- Definition Classes
- Area → Nameable → AnyRef → Any
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def
unsetName(): BusSlaveFactory.this.type
- Definition Classes
- Nameable
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final
def
wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws( ... )
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final
def
wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @throws( ... )
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def
wordAddressInc: Int
Address incrementation used by the read and write multi words registers
- def write[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
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def
write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
When the bus write the address, assign that with bus’s data from bitOffset
- def writeAddress(address: AddressMapping): UInt
- def writeMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]
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def
writeMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to write that at address.
Create the memory mapping to write that at address. If that is bigger than one word it extends the register on followings addresses
Deprecated Value Members
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def
createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
- Annotations
- @deprecated
- Deprecated
Use createReadAndWrite instead