case class RiscvCoreConfig(pcWidth: Int = 32, addrWidth: Int = 32, startAddress: BigInt = 0, bypassExecute0: Boolean = true, bypassExecute1: Boolean = true, bypassWriteBack: Boolean = true, bypassWriteBackBuffer: Boolean = true, collapseBubble: Boolean = true, branchPrediction: BranchPrediction = static, regFileReadyKind: RegFileReadKind = sync, fastFetchCmdPcCalculation: Boolean = true, dynamicBranchPredictorCacheSizeLog2: Int = 4, branchPredictorHistoryWidth: Int = 2, invalidInstructionIrqId: Int = 0, unalignedMemoryAccessIrqId: Int = 1) extends Product with Serializable
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- new RiscvCoreConfig(pcWidth: Int = 32, addrWidth: Int = 32, startAddress: BigInt = 0, bypassExecute0: Boolean = true, bypassExecute1: Boolean = true, bypassWriteBack: Boolean = true, bypassWriteBackBuffer: Boolean = true, collapseBubble: Boolean = true, branchPrediction: BranchPrediction = static, regFileReadyKind: RegFileReadKind = sync, fastFetchCmdPcCalculation: Boolean = true, dynamicBranchPredictorCacheSizeLog2: Int = 4, branchPredictorHistoryWidth: Int = 2, invalidInstructionIrqId: Int = 0, unalignedMemoryAccessIrqId: Int = 1)
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- def add[T <: CoreExtension](that: T): T
- val addrWidth: Int
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- val branchPrediction: BranchPrediction
- val branchPredictorHistoryWidth: Int
- val bypassExecute0: Boolean
- val bypassExecute1: Boolean
- val bypassWriteBack: Boolean
- val bypassWriteBackBuffer: Boolean
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- val collapseBubble: Boolean
- val dynamicBranchPredictorCacheSizeLog2: Int
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- val extensions: ArrayBuffer[CoreExtension]
- val fastFetchCmdPcCalculation: Boolean
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- val invalidInstructionIrqId: Int
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- val pcWidth: Int
- def productElementNames: Iterator[String]
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- Product
- val regFileReadyKind: RegFileReadKind
- val startAddress: BigInt
- final def synchronized[T0](arg0: => T0): T0
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- val unalignedMemoryAccessIrqId: Int
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