case class AxiMemorySim(axi: Axi4, clockDomain: ClockDomain, config: AxiMemorySimConfig) extends Product with Serializable
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Instance Constructors
- new AxiMemorySim(axi: Axi4, clockDomain: ClockDomain, config: AxiMemorySimConfig)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val axi: Axi4
- val busWordWidth: Int
Bus word width in bytes
- val clockDomain: ClockDomain
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- val config: AxiMemorySimConfig
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def getBurst(ax: Axi4Ax): Int
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getId(ax: Axi4Ax): Long
- def getLen(ax: Axi4Ax): Int
- def getSize(ax: Axi4Ax): Int
- def getSizeAndCheck(ax: Axi4Ax): Int
- def getStrb(w: Axi4W): BigInt
- def handleAr(ar: Stream[Axi4Ar]): Unit
- def handleAw(aw: Stream[Axi4Aw]): Unit
- def handleAwAndW(w: Stream[Axi4W], aw: Stream[Axi4Aw], b: Stream[Axi4B]): Unit
Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform.
Handle write command, write, and write response channel as implemented by Altera/Intel on their Cyclone 5 platform. Their implementation behaves as all three channels are coupled. The implementation waits until all words for a write operation have been transfered. Then it asserts the AWREADY to accept the write command. After that, BVALID is asserted.
- w
AXI write channel
- aw
AXI write command channel
- b
AXI write response channel
- def handleR(r: Stream[Axi4R]): Unit
- def handleW(w: Stream[Axi4W], b: Stream[Axi4B]): Unit
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val maxBurstSize: Int
- val memory: SparseMemory
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def newAxiJob(ax: Axi4Ax): AxiJob
- def newAxiJob(address: Long, burstLength: Int, burstSize: Int, burstType: Int, id: Long): AxiJob
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- val pending_reads: Queue[AxiJob]
- val pending_writes: Queue[AxiJob]
- def productElementNames: Iterator[String]
- Definition Classes
- Product
- def reset(): Unit
- def setLast(r: Axi4R, last: Boolean): Unit
- def start(): Unit
- def stop(): Unit
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val threads: Queue[SimThread]
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
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- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated