trait BusSlaveFactory extends Area
Bus slave factory is a tool that provide an abstract and smooth way to define register bank
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- abstract type RefOwnerType
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Abstract Value Members
- abstract def busDataWidth: Int
Return the data width of the bus
- abstract def nonStopWrite[T <: Data](that: T, bitOffset: Int = 0, documentation: String = null): T
Permanently assign that by the bus write data from bitOffset
- abstract def onReadPrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: => Unit): Unit
- abstract def onWritePrimitive(address: AddressMapping, haltSensitive: Boolean, documentation: String)(doThat: => Unit): Unit
- abstract def readAddress(): UInt
- abstract def readHalt(): Unit
- abstract def readPrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
- abstract def writeAddress(): UInt
- abstract def writeHalt(): Unit
- abstract def writePrimitive[T <: Data](that: T, address: AddressMapping, bitOffset: Int, documentation: String): Unit
Concrete Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
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- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- val _config: BusSlaveFactoryConfig
Configuration of the BusSlaveFactory
Configuration of the BusSlaveFactory
- Attributes
- protected
- val _context: Capture
- Definition Classes
- Area
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def childNamePriority: Byte
- Definition Classes
- Area
- def clearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
- def clone(): AnyRef
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- protected[lang]
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def component: Component
- Definition Classes
- ContextUser
- def createAndDriveFlow[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): Flow[T]
Create a writable Flow register of type dataType at address and placed at bitOffset in the word
- def createReadAndClearOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
- def createReadAndSetOnSet[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
- def createReadAndWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a read write register of type dataType at address and placed at bitOffset in the word
- def createReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words read register of type dataType
- def createReadOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a read only register of type dataType at address and placed at bitOffset in the word
- def createWriteAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words write and read register of type dataType
- def createWriteMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Create multi-words write register of type dataType
- def createWriteOnly[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Create a write only register of type dataType at address and placed at bitOffset in the word
- def doBitsAccumulationAndClearOnRead(that: Bits, address: BigInt, bitOffset: Int = 0): Unit
Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared.
Instantiate an internal register which at each cycle do : reg := reg | that Then when a read occur, the register is cleared. This register is readable at address and placed at bitOffset in the word
- def drive[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
- def drive[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Drive that with a register writable at address placed at bitOffset in the word
- def driveAndRead[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
Drive that with a register writable and readable at address placed at bitOffset in the word
- def driveAndReadMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Drive and read that on multi-word
- def driveFlow[T <: Data](that: Flow[T], address: BigInt, bitOffset: Int = 0): Unit
Emit on that a transaction when a write happen at address by using data placed at bitOffset in the word
- def driveMultiWord[T <: Data](that: T, address: BigInt, documentation: String = null): T
Drive that on multi-words
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
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- def equals(obj: Any): Boolean
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- OverridedEqualsHashCode → AnyRef → Any
- def foreachReflectableNameables(doThat: (Any) => Unit): Unit
- Definition Classes
- Nameable
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getConfig: BusSlaveFactoryConfig
- def getDisplayName(): String
- Definition Classes
- Nameable
- def getInstanceCounter: Int
- Definition Classes
- ContextUser
- def getMode: Byte
- Attributes
- protected
- Definition Classes
- Nameable
- def getName(default: String): String
- Definition Classes
- NameableByComponent → Nameable
- def getName(): String
- Definition Classes
- NameableByComponent → Nameable
- def getPartialName(): String
- Definition Classes
- Nameable
- def getRefOwnersChain(): List[Any]
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- OwnableRef
- def getScalaLocationLong: String
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- ScalaLocated
- def getScalaLocationShort: String
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- ScalaLocated
- def getScalaTrace(): Throwable
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- ScalaLocated
- val globalData: GlobalData
- Definition Classes
- GlobalDataUser
- def hashCode(): Int
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- OverridedEqualsHashCode → AnyRef → Any
- def isCompletelyUnnamed: Boolean
- Definition Classes
- Nameable
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isNamed: Boolean
- Definition Classes
- NameableByComponent → Nameable
- def isPriorityApplicable(namePriority: Byte): Boolean
- Definition Classes
- Nameable
- def isReading(address: BigInt): Bool
Return true if the bus is reading
- def isUnnamed: Boolean
- Definition Classes
- Nameable
- def isWriting(address: BigInt): Bool
Return true if the bus is writing
- def multiCycleRead(address: AddressMapping, cycles: BigInt): Unit
- val name: String
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- Nameable
- val nameableRef: Nameable
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- protected
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- @DontName()
- final def ne(arg0: AnyRef): Boolean
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- final def notify(): Unit
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- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
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- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def onRead(address: BigInt, documentation: String = null)(doThat: => Unit): Unit
Call doThat when a read transaction occurs on address
- def onWrite(address: BigInt, documentation: String = null)(doThat: => Unit): Unit
Call doThat when a write transaction occurs on address
- def overrideLocalName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- val parentScope: ScopeStatement
- Definition Classes
- ContextUser
- def read[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
- def read[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
When the bus read the address, fill the response with that at bitOffset
- def readAddress(address: AddressMapping): UInt
- def readAndClearOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
- def readAndSetOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
- def readAndWrite(that: Data, address: BigInt, bitOffset: Int = 0, documentation: String = null): Unit
Make that readable and writable at address and placed at bitOffset in the word
- def readAndWriteMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to write/read that from address
- def readFire(): Bool
- def readMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to read
that
fromaddress
Ifthat
is bigger than one word it extends the register on following addresses. - def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt, validBitOffset: Int, payloadBitOffset: Int, validInverted: Boolean = false): Unit
Read that and consume the transaction when a read happen at address.
- def readStreamNonBlocking[T <: Data](that: Stream[T], address: BigInt): Unit
Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.
Read that (that is bigger than the busWidth) and consume the transaction when a read happen at address.
- Note
in order to avoid to read wrong data read first the address which contains the valid signal. Little : payload - valid at address 0x00 Big : valid - payload at address 0x00 Once the valid signal is true you can read all registers
- def readSyncMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]
Memory map a Mem to bus for reading.
Memory map a Mem to bus for reading. Elements can be larger than bus data width in bits.
- def readSyncMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]
- val refOwner: RefOwnerType
- Definition Classes
- OwnableRef
- Annotations
- @DontName()
- def reflectNames(): Unit
- Definition Classes
- Nameable
- def rework[T](body: => T): T
- Definition Classes
- Area
- val scalaTrace: Throwable
- Definition Classes
- ScalaLocated
- def setCompositeName(nameable: Nameable, postfix: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, postfix: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, postfix: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setCompositeName(nameable: Nameable): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setConfig(value: BusSlaveFactoryConfig): BusSlaveFactory.this.type
- def setName(name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setName(name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setNameAsWeak(): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setOnClear[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
- def setOnSet[T <: Data](that: T, address: BigInt, bitOffset: Int = 0): T
- def setPartialName(name: String, namePriority: Byte, owner: Any): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String, namePriority: Byte): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String, weak: Boolean): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setPartialName(owner: Nameable, name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setRefOwner(that: Any): Unit
- Definition Classes
- OwnableRef
- def setScalaLocated(source: ScalaLocated): BusSlaveFactory.this.type
- Definition Classes
- ScalaLocated
- def setWeakName(name: String): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def setWordEndianness(value: Endianness): BusSlaveFactory
Set the endianness during write/read multiword
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- def toString(): String
- Definition Classes
- Area → Nameable → AnyRef → Any
- def unsetName(): BusSlaveFactory.this.type
- Definition Classes
- Nameable
- def valCallback[T](ref: T, name: String): T
- Definition Classes
- ValCallbackRec → ValCallback
- def valCallbackOn(ref: Any, name: String, refs: Set[Any]): Unit
- Definition Classes
- ValCallbackRec
- def valCallbackRec(obj: Any, name: String): Unit
- Definition Classes
- Area → ValCallbackRec
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def withOffset(offset: Int): BusSlaveFactoryAddressWrapper
- def wordAddressInc: Int
Address incrementation used by the read and write multi words registers
- def write[T <: Data](address: BigInt, bitMapping: (Int, Data)*): Unit
- def write[T <: Data](that: T, address: BigInt, bitOffset: Int = 0, documentation: String = null): T
When the bus write the address, assign that with bus’s data from bitOffset
- def writeAddress(address: AddressMapping): UInt
- def writeByteEnable(): Bits
Byte enable bits, defaulting to all ones
- def writeFire(): Bool
- def writeMemMultiWord[T <: Data](mem: Mem[T], addressOffset: BigInt): Mem[T]
Memory map a Mem to bus for writing.
Memory map a Mem to bus for writing. Elements can be larger than bus data width in bits.
- def writeMemWordAligned[T <: Data](mem: Mem[T], addressOffset: BigInt, bitOffset: Int = 0): Mem[T]
- def writeMultiWord(that: Data, address: BigInt, documentation: String = null): Unit
Create the memory mapping to write that at address.
Create the memory mapping to write that at address. If
that
is bigger than one word it extends the register on following addresses.
Deprecated Value Members
- def createReadWrite[T <: Data](dataType: T, address: BigInt, bitOffset: Int = 0): T
- Annotations
- @deprecated
- Deprecated
(Since version ???) Use createReadAndWrite instead
- def finalize(): Unit
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- protected[lang]
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- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated