final case classGate(rate: Rate, in: GE, gate: GE) extends SingleOut with Product with Serializable
A gate or hold UGen. It allows the input signal value to pass when the gate
argument is positive, otherwise it holds last value.
in
the input signal to gate
gate
the signal specifying whether to pass the input signal
(when greater than zero) or whether to close the gate
and hold the last value (when less than or equal to zero)
the signal specifying whether to pass the input signal
(when greater than zero) or whether to close the gate
and hold the last value (when less than or equal to zero)
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valgate: GE
the signal specifying whether to pass the input signal
(when greater than zero) or whether to close the gate
and hold the last value (when less than or equal to zero)
A gate or hold UGen. It allows the input signal value to pass when the
gate
argument is positive, otherwise it holds last value.the input signal to gate
the signal specifying whether to pass the input signal (when greater than zero) or whether to close the gate and hold the last value (when less than or equal to zero)
de.sciss.synth.ugen.Latch