abstract class OrderedDecoupledHWIOTester extends HWIOTester

Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated

Source
OrderedDecoupledHWIOTester.scala
Example: 

  1. class XTimesXTester extends [[OrderedDecoupledHWIOTester]] {
  val device_under_test = new XTimesY
  test_block {
    for {
      i <- 0 to 10
      j <- 0 to 10
    } {
      input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j)
      output_event(device_under_test.io.out.z -> i*j)
    }
  }
}

    an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created

Linear Supertypes
HWIOTester, BasicTester, LegacyModule, ImplicitModule, UserModule, BaseModule, HasId, InstanceId, AnyRef, Any
Type Hierarchy
Ordering
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Inherited
  1. OrderedDecoupledHWIOTester
  2. HWIOTester
  3. BasicTester
  4. LegacyModule
  5. ImplicitModule
  6. UserModule
  7. BaseModule
  8. HasId
  9. InstanceId
  10. AnyRef
  11. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new OrderedDecoupledHWIOTester()

Type Members

  1. class GlobalEventCounter extends AnyRef
  2. case class TestingEvent (port_values: Map[Data, BigInt], event_number: Int) extends Product with Serializable

Abstract Value Members

  1. abstract val device_under_test: Module
    Definition Classes
    HWIOTester

Concrete Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: core.Data](iodef: T): iodef.type
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _autoWrapPorts(): Unit
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _ioPortBound(): Boolean
    Attributes
    protected
    Definition Classes
    LegacyModule
  8. def annotate(annotation: ChiselAnnotation): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, BigInt)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

    Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes

  11. val clock: core.Clock
    Definition Classes
    ImplicitModule
  12. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  13. val compileOptions: CompileOptions
    Definition Classes
    UserModule
  14. val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
  15. val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
  16. def desiredName: String
    Definition Classes
    BaseModule
  17. var enable_all_debug: Boolean
    Definition Classes
    HWIOTester
  18. var enable_printf_debug: Boolean
    Definition Classes
    HWIOTester
  19. var enable_scala_debug: Boolean
    Definition Classes
    HWIOTester
  20. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  21. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  22. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  23. def finish(): Unit

    this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

    this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid

    Definition Classes
    OrderedDecoupledHWIOTester → HWIOTester → BasicTester
  24. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
  25. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    UserModule
  26. def getCommonValidParentPort(expects: Seq[(Data, BigInt)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]

    Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes

  27. def getIds: Seq[HasId]
    Attributes
    protected
    Definition Classes
    BaseModule
  28. def getModulePorts: Seq[core.Data]
    Attributes
    protected
    Definition Classes
    BaseModule
  29. lazy val getPorts: Seq[Port]
    Definition Classes
    UserModule
  30. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  31. def inputEvent(pokes: (Data, BigInt)*): Unit
  32. val input_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
  33. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  34. val io: core.Bundle
    Definition Classes
    BasicTester → LegacyModule
  35. var io_info: IOAccessor
    Definition Classes
    HWIOTester
  36. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  37. def logPrintfDebug(fmt: String, args: Bits*): Unit
    Definition Classes
    HWIOTester
  38. def logScalaDebug(msg: ⇒ String): Unit
    Definition Classes
    HWIOTester
  39. final val name: String
    Definition Classes
    BaseModule
  40. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    LegacyModule → BaseModule
  41. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  42. final def notify(): Unit
    Definition Classes
    AnyRef
  43. final def notifyAll(): Unit
    Definition Classes
    AnyRef
  44. def outputEvent(expects: (Data, BigInt)*): Unit
  45. val output_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
  46. var override_clock: Option[core.Clock]
    Attributes
    protected
    Definition Classes
    LegacyModule
  47. var override_reset: Option[core.Bool]
    Attributes
    protected
    Definition Classes
    LegacyModule
  48. def parentModName: String
    Definition Classes
    HasId → InstanceId
  49. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  50. def pathName: String
    Definition Classes
    HasId → InstanceId
  51. def popCount(n: Long): Int
    Definition Classes
    BasicTester
  52. val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]
  53. val port_to_valid: HashMap[Data, ValidIO[Data]]
  54. def portsContains(elem: core.Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  55. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  56. def processInputEvents(): Unit

    iterate over recorded events, checking constraints on ports referenced, etc.

    iterate over recorded events, checking constraints on ports referenced, etc. use poke and expect to record

  57. def processOutputEvents(): Unit
  58. val reset: Reset
    Definition Classes
    ImplicitModule
  59. val rnd: Random.type
    Definition Classes
    HWIOTester
  60. def stop()(implicit sourceInfo: SourceInfo): Unit
    Definition Classes
    BasicTester
  61. def suggestName(name: ⇒ String): OrderedDecoupledHWIOTester.this.type
    Definition Classes
    HasId
  62. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  63. def toString(): String
    Definition Classes
    AnyRef → Any
  64. val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]
  65. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  66. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  67. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from HWIOTester

Inherited from BasicTester

Inherited from LegacyModule

Inherited from ImplicitModule

Inherited from UserModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped