Type Members

1.  abstract class AdvTester[+T <: Module] extends PeekPokeTester[T]
2.  trait AdvTests extends PeekPokeTests
3.  class ChiselFlatSpec extends FlatSpec with ChiselRunners with Matchers

   Spec base class for BDD-style testers.

4.  class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks

   Spec base class for property-based testers.

5.  trait ChiselRunners extends Assertions

   Common utility functions for Chisel unit tests.

6.  class CommandEditor extends AnyRef

   This function applies a last chance method of making final alteration of the vcs command line.

   This function applies a last chance method of making final alteration of the vcs command line. Alterations are made from a text file containing ed style regex substitutions s/regex-pattern/substitution/ or more generally s<<separator>>regex-pattern<<separator>>substitution<<separator>> if the file begins with the line verbose, the substitution parsing and operation will be logged to stdout

7.  abstract class Exerciser extends BasicTester

   experimental version of a Tester that allows arbitrary testing circuitry to be run in some order

8.  abstract class HWIOTester extends BasicTester

   provide common facilities for step based testing and decoupled interface testing

9.  trait HasTesterOptions extends AnyRef
10.  class IOAccessor extends AnyRef

    named access and type information about the IO bundle of a module used for building testing harnesses

11.  abstract class OrderedDecoupledHWIOTester extends HWIOTester

    Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported.

    Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated

    Example:

    1. class XTimesXTester extends [[OrderedDecoupledHWIOTester]] {
         val device_under_test = new XTimesY
         test_block {
           for {
             i <- 0 to 10
             j <- 0 to 10
           } {
             input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j)
             output_event(device_under_test.io.out.z -> i*j)
           }
         }
       }

       an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created

12.  abstract class PeekPokeTester[+T <: MultiIOModule] extends AnyRef
13.  trait PeekPokeTests extends AnyRef
14.  trait Processable extends AnyRef
15.  class ReplOptionsManager extends InterpreterOptionsManager with HasChiselExecutionOptions with HasReplConfig
16.  abstract class SteppedHWIOTester extends HWIOTester

    Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes

    Use a UnitTester to construct a test harness for a chisel module this module will be canonically referred to as the device_under_test, often simply as c in a unit test, and also dut The UnitTester is used to put series of values (as chisel3.Vec's) into the ports of the dut io which are INPUT At specified times it check the dut io OUTPUT ports to see that they match a specific value The vec's are assembled through the following API poke, expect and step, pokes

    Example:

    1. class Adder(width:Int) extends Module {
         val io = new Bundle {
           val in0 : UInt(INPUT, width=width)
           val in1 : UInt(INPUT, width=width)
           val out : UInt(OUTPUT, width=width)
         }
       }
       class AdderTester extends UnitTester {
         val device_under_test = Module( new Adder(32) )
       
         testBlock {
           poke(c.io.in0, 5)
           poke(c.io.in1, 7)
           expect(c.io.out, 12)
         }
       }

17.  case class TesterOptions(isGenVerilog: Boolean = false, isGenHarness: Boolean = false, isCompiling: Boolean = false, isRunTest: Boolean = false, isVerbose: Boolean = false, displayBase: Int = 10, testerSeed: Long = System.currentTimeMillis, testCmd: Seq[String] = Seq.empty, moreVcsFlags: Seq[String] = Seq.empty, moreVcsCFlags: Seq[String] = Seq.empty, vcsCommandEdits: String = "", backendName: String = "firrtl", logFileName: String = "", waveform: Option[File] = None) extends ComposableOptions with Product with Serializable
18.  class TesterOptionsManager extends ExecutionOptionsManager with HasTesterOptions with HasInterpreterSuite with HasChiselExecutionOptions with HasFirrtlOptions