The "strong connect" operator.

For chisel3._, this operator is mono-directioned; all sub-elements of this will be driven by sub-elements of that.

• Equivalent to this :#= that

For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=

• Equivalent to this :<>= that

The "bulk connect operator", assigning elements in this Vec from elements in a Vec.

For chisel3._, uses the chisel3.internal.BiConnect algorithm; sub-elements of that may end up driving sub-elements of this

• Complicated semantics, hard to write quickly, will likely be deprecated in the future

For Chisel._, emits the FIRRTL.<- operator

• Equivalent to this :<>= that without the restrictions that bundle field names and vector sizes must match

Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin

This method is implemented by the compiler plugin

Indicates if a concrete Bundle class was compiled using the compiler plugin

Used for optimizing Chisel's performance and testing Chisel itself

Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.

x.asTypeOf(that) performs the inverse operation of x := that.toBits.

Reinterpret cast to UInt.

Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).

If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.

Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.

Name for Pretty Printing

Internal API; Chisel users should look at chisel3.chiselTypeOf(...).

cloneType must be defined for any Chisel object extending Data. It is responsible for constructing a basic copy of the object being cloned.

The collection of Data

Elements defined earlier in the Bundle are higher order upon serialization. For example:

Returns a Seq of the immediate contents of this Aggregate, in order.

Returns the width, in bits, if currently known.

Returns whether the width is currently known.

Return an Aggregate's literal value if it is a literal, None otherwise. If any element of the aggregate is not a literal with a defined width, the result isn't a literal.

Returns the literal value if this is a literal that is representable as bits, otherwise crashes.

Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

Returns a FIRRTL ComponentName that references this object

Default "pretty-print" implementation Analogous to printing a Map Results in "Bundle(elt0.name -> elt0.value, ...)"

The collection of chisel3.Data

This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to Vec). For example:

// Assume we have some type MyRecord that creates a Record from the ListMap
val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W)))
// "buzz" is higher order because it was added later than "fizz"
record("fizz") := "hdead".U
record("buzz") := "hbeef".U
val uint = record.asUInt
assert(uint === "hbeefdead".U) // This will pass

Returns a FIRRTL ReferenceTarget that references this object

Returns Some(width) if the width is known, else None.