Pipe

Pipeline module generator parameterized by data type and latency.

This defines a module with one input, enq, and one output, deq. The input and output are Valid interfaces that wrap some Chisel type, e.g., a UInt or a Bundle. This generator will then chain together a number of pipeline stages that all advance when the input Valid enq fires. The output deq Valid will fire only when valid data has made it all the way through the pipeline.

As an example, to construct a 4-stage pipe of 8-bit UInts and connect it to a producer and consumer, you can use the following:

val foo = Module(new Pipe(UInt(8.W)), 4)
pipe.io.enq := producer.io
consumer.io := pipe.io.deq

If you already have the Valid input or the components of a Valid interface, it may be simpler to use the Pipe factory companion object. This, which Pipe internally utilizes, will automatically connect the input for you.

Source: Valid.scala
See also: The ShiftRegister factory to generate a pipe without a Valid interface
Queue and the Queue factory for actual queues
Valid interface
Pipe factory for an alternative API

Linear Supertypes

LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, internal.InstanceId, AnyRef, Any

Type Hierarchy

Instance Constructors

new Pipe(gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions)

gen
a Chisel type
latency
the number of pipeline stages

Type Members

class PipeIO extends Bundle

Interface for Pipes composed of a Valid input and Valid output

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: Data](iodef: T): T

Attributes
protected
Definition Classes
BaseModule
def _bindIoInPlace(iodef: Data): Unit

Attributes
protected
Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _compatAutoWrapPorts(): Unit

Definition Classes
BaseModule
def _compatIoPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
final def asInstanceOf[T0]: T0

Definition Classes
Any
def circuitName: String

Attributes
protected
Definition Classes
HasId
final val clock: Clock

Definition Classes
MultiIOModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compileOptions: CompileOptions

Definition Classes
RawModule
def desiredName: String

Definition Classes
BaseModule
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
RawModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[Data]

Attributes
protected[chisel3]
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
RawModule
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
val io: PipeIO

Definition Classes
Pipe → LegacyModule
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
final lazy val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
var override_clock: Option[Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[Bool]

Attributes
protected
Definition Classes
LegacyModule
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
final val reset: Reset

Definition Classes
MultiIOModule
def suggestName(name: ⇒ String): Pipe.this.type

Definition Classes
HasId
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
final def toAbsoluteTarget: IsModule

Definition Classes
BaseModule → InstanceId
final def toNamed: ModuleName

Definition Classes
BaseModule → InstanceId
def toString(): String

Definition Classes
AnyRef → Any
final def toTarget: ModuleTarget

Definition Classes
BaseModule → InstanceId
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )

Related Docs: object Pipe | package util

class Pipe[T <: Data] extends Module

Instance Constructors

new Pipe(gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions)

Type Members

class PipeIO extends Bundle

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): T

def _bindIoInPlace(iodef: Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

def _compatIoPortBound(): Boolean

final def asInstanceOf[T0]: T0

def circuitName: String

final val clock: Clock

def clone(): AnyRef

val compileOptions: CompileOptions

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

val io: PipeIO

final def isInstanceOf[T0]: Boolean

final lazy val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def notify(): Unit

final def notifyAll(): Unit

var override_clock: Option[Clock]

var override_reset: Option[Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

final val reset: Reset

def suggestName(name: ⇒ String): Pipe.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

final def toAbsoluteTarget: IsModule

final def toNamed: ModuleName

def toString(): String

final def toTarget: ModuleTarget

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped