FibonacciLFSR

Fibonacci Linear Feedback Shift Register (LFSR) generator.

A Fibonacci LFSR can be generated by defining a width and a set of tap points (corresponding to a polynomial). An optional initial seed and a reduction operation (XOR, the default, or XNOR) can be used to augment the generated hardware. The resulting hardware has support for a run-time programmable seed (via PRNGIO.seed) and conditional increment (via PRNGIO.increment).

If the user specifies a seed, then a compile-time check is added that they are not initializing the LFSR to a state which will cause it to lock up. If the user does not set a seed, then the least significant bit of the state will be set or reset based on the choice of reduction operator.

In the example below, a 4-bit Fibonacci LFSR is constructed. Tap points are defined as four and three (using LFSR convention of indexing from one). This results in the hardware configuration shown in the diagram.

val lfsr4 = Module(new FibonacciLFSR(4, Set(4, 3))
//                 +---+
// +-------------->|XOR|-------------------------------------------------------+
// |               +---+                                                       |
// |   +-------+     ^     +-------+           +-------+           +-------+   |
// |   |       |     |     |       |           |       |           |       |   |
// +---+  x^4  |<----+-----|  x^3  |<----------|  x^2  |<----------|  x^1  |<--+
//     |       |           |       |           |       |           |       |
//     +-------+           +-------+           +-------+           +-------+

If you require a maximal period Fibonacci LFSR of a specific width, you can use MaxPeriodFibonacciLFSR. If you only require a pseudorandom UInt you can use the FibonacciLFSR companion object.

Source: FibonacciLFSR.scala
See also: https://en.wikipedia.org/wiki/Linear-feedback_shift_register#Fibonacci_LFSRs

Linear Supertypes

LFSR, PRNG, LegacyModule, MultiIOModule, RawModule, BaseModule, HasId, internal.InstanceId, AnyRef, Any

Known Subclasses

MaxPeriodFibonacciLFSR

Type Hierarchy

Instance Constructors

new FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)

width
the width of the LFSR
taps
a set of tap points to use when constructing the LFSR
seed
an initial value for internal LFSR state. If None, then the LFSR state LSB will be set to a known safe value on reset (to prevent lock up).
reduction
the reduction operation (either XOR or XNOR)
step
the number of state updates per cycle
updateSeed
if true, when loading the seed the state will be updated as if the seed were the current state, if false, the state will be set to the seed

Value Members

final def !=(arg0: Any): Boolean

Definition Classes
AnyRef → Any
final def ##(): Int

Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean

Definition Classes
AnyRef → Any
def IO[T <: Data](iodef: T): T

Attributes
protected
Definition Classes
BaseModule
def _bindIoInPlace(iodef: Data): Unit

Attributes
protected
Definition Classes
BaseModule
var _closed: Boolean

Attributes
protected
Definition Classes
BaseModule
def _compatAutoWrapPorts(): Unit

Definition Classes
BaseModule
def _compatIoPortBound(): Boolean

Attributes
protected
Definition Classes
LegacyModule
final def asInstanceOf[T0]: T0

Definition Classes
Any
def circuitName: String

Attributes
protected
Definition Classes
HasId
final val clock: Clock

Definition Classes
MultiIOModule
def clone(): AnyRef

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( ... )
val compileOptions: CompileOptions

Definition Classes
RawModule
def delta(s: Seq[Bool]): Seq[Bool]

State update function
State update function
s
input state
returns
the next state

Definition Classes
FibonacciLFSR → PRNG
def desiredName: String

Definition Classes
BaseModule
final def eq(arg0: AnyRef): Boolean

Definition Classes
AnyRef
def equals(that: Any): Boolean

Definition Classes
HasId → AnyRef → Any
def finalize(): Unit

Attributes
protected[java.lang]
Definition Classes
AnyRef
Annotations
@throws( classOf[java.lang.Throwable] )
final def getClass(): Class[_]

Definition Classes
AnyRef → Any
def getCommands: Seq[Command]

Attributes
protected
Definition Classes
RawModule
def getIds: Seq[HasId]

Attributes
protected
Definition Classes
BaseModule
def getModulePorts: Seq[Data]

Attributes
protected[chisel3]
Definition Classes
BaseModule
lazy val getPorts: Seq[Port]

Definition Classes
RawModule
def hashCode(): Int

Definition Classes
HasId → AnyRef → Any
def instanceName: String

Definition Classes
BaseModule → HasId → InstanceId
val io: PRNGIO

Definition Classes
PRNG → LegacyModule
final def isInstanceOf[T0]: Boolean

Definition Classes
Any
final lazy val name: String

Definition Classes
BaseModule
def nameIds(rootClass: Class[_]): HashMap[HasId, String]

Attributes
protected
Definition Classes
BaseModule
final def ne(arg0: AnyRef): Boolean

Definition Classes
AnyRef
final def nextState(s: Seq[Bool]): Seq[Bool]

The method that will be used to update the state of this PRNG
The method that will be used to update the state of this PRNG
s
input state
returns
the next state after step applications of PRNG.delta

Definition Classes
PRNG
final def notify(): Unit

Definition Classes
AnyRef
final def notifyAll(): Unit

Definition Classes
AnyRef
var override_clock: Option[Clock]

Attributes
protected
Definition Classes
LegacyModule
var override_reset: Option[Bool]

Attributes
protected
Definition Classes
LegacyModule
def parentModName: String

Definition Classes
HasId → InstanceId
def parentPathName: String

Definition Classes
HasId → InstanceId
def pathName: String

Definition Classes
HasId → InstanceId
def portsContains(elem: Data): Boolean

Attributes
protected
Definition Classes
BaseModule
def portsSize: Int

Attributes
protected
Definition Classes
BaseModule
val reduction: LFSRReduce

the reduction operation (either XOR or XNOR)
the reduction operation (either XOR or XNOR)

Definition Classes
FibonacciLFSR → LFSR
final val reset: Reset

Definition Classes
MultiIOModule
def resetValue: Vec[Bool]

Allow implementations to override the reset value, e.g., if some bits should be don't-cares.
Allow implementations to override the reset value, e.g., if some bits should be don't-cares.

Attributes
protected
Definition Classes
LFSR → PRNG
val seed: Option[BigInt]

the initial state of the PRNG
the initial state of the PRNG

Definition Classes
PRNG
def suggestName(name: ⇒ String): FibonacciLFSR.this.type

Definition Classes
HasId
final def synchronized[T0](arg0: ⇒ T0): T0

Definition Classes
AnyRef
final def toAbsoluteTarget: IsModule

Definition Classes
BaseModule → InstanceId
final def toNamed: ModuleName

Definition Classes
BaseModule → InstanceId
def toString(): String

Definition Classes
AnyRef → Any
final def toTarget: ModuleTarget

Definition Classes
BaseModule → InstanceId
final def wait(): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long, arg1: Int): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
final def wait(arg0: Long): Unit

Definition Classes
AnyRef
Annotations
@throws( ... )
val width: Int

the width of the PRNG
the width of the PRNG

Definition Classes
PRNG

Related Docs: object FibonacciLFSR | package random

class FibonacciLFSR extends PRNG with LFSR

Instance Constructors

new FibonacciLFSR(width: Int, taps: Set[Int], seed: Option[BigInt] = Some(1), reduction: LFSRReduce = XOR, step: Int = 1, updateSeed: Boolean = false)

Value Members

final def !=(arg0: Any): Boolean

final def ##(): Int

final def ==(arg0: Any): Boolean

def IO[T <: Data](iodef: T): T

def _bindIoInPlace(iodef: Data): Unit

var _closed: Boolean

def _compatAutoWrapPorts(): Unit

def _compatIoPortBound(): Boolean

final def asInstanceOf[T0]: T0

def circuitName: String

final val clock: Clock

def clone(): AnyRef

val compileOptions: CompileOptions

def delta(s: Seq[Bool]): Seq[Bool]

def desiredName: String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

final def getClass(): Class[_]

def getCommands: Seq[Command]

def getIds: Seq[HasId]

def getModulePorts: Seq[Data]

lazy val getPorts: Seq[Port]

def hashCode(): Int

def instanceName: String

val io: PRNGIO

final def isInstanceOf[T0]: Boolean

final lazy val name: String

def nameIds(rootClass: Class[_]): HashMap[HasId, String]

final def ne(arg0: AnyRef): Boolean

final def nextState(s: Seq[Bool]): Seq[Bool]

final def notify(): Unit

final def notifyAll(): Unit

var override_clock: Option[Clock]

var override_reset: Option[Bool]

def parentModName: String

def parentPathName: String

def pathName: String

def portsContains(elem: Data): Boolean

def portsSize: Int

val reduction: LFSRReduce

final val reset: Reset

def resetValue: Vec[Bool]

val seed: Option[BigInt]

def suggestName(name: ⇒ String): FibonacciLFSR.this.type

final def synchronized[T0](arg0: ⇒ T0): T0

final def toAbsoluteTarget: IsModule

final def toNamed: ModuleName

def toString(): String

final def toTarget: ModuleTarget

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val width: Int

Inherited from LFSR

Inherited from PRNG

Inherited from LegacyModule

Inherited from MultiIOModule

Inherited from RawModule

Inherited from BaseModule

Inherited from HasId

Inherited from internal.InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped