object Pipe
A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.
Example usage: val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt,SInt,Bool,FixedPoint,Clock, andReg, the abstract typesBits,Aggregate, andData, and the aggregate typesBundleandVec.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
utilpackage.The
testerspackage defines the basic interface for chisel testers.