Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, FixedPoint, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3

    The chisel3 package contains the chisel3 API.

    The chisel3 package contains the chisel3 API. It maps core components into the public chisel3 namespace.

    Definition Classes
    root
  • package util

    The util package provides extensions to core chisel for common hardware components and utility functions

    The util package provides extensions to core chisel for common hardware components and utility functions

    Definition Classes
    chisel3
  • package experimental
    Definition Classes
    util
  • ChiselLoadMemoryAnnotation
  • LoadMemoryTransform
  • loadMemoryFromFile
p

chisel3.util

experimental

package experimental

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Visibility
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Type Members

  1. case class ChiselLoadMemoryAnnotation[T <: Data](target: MemBase[T], fileName: String, hexOrBinary: FileType = MemoryLoadFileType.Hex) extends ChiselAnnotation with RunFirrtlTransform with Product with Serializable

    This is the annotation created when using loadMemoryFromFile, it records the memory, the load file and the format of the file.

    This is the annotation created when using loadMemoryFromFile, it records the memory, the load file and the format of the file.

    target

    memory to load

    fileName

    name of input file

    hexOrBinary

    use $readmemh or $readmemb, i.e. hex or binary text input, default is hex

  2. class LoadMemoryTransform extends Transform

    This transform only is activated if verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional verilog files that contain modules bound to the modules that contain an initializable memory

    This transform only is activated if verilog is being generated (determined by presence of the proper emit annotation) when activated it creates additional verilog files that contain modules bound to the modules that contain an initializable memory

    Currently the only non-verilog based simulation that can support loading memory from a file is treadle but it does not need this transform to do that.

Value Members

  1. object loadMemoryFromFile

Ungrouped