class ChiselStage extends Stage with PreservesAll[Phase]
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Instance Constructors
- new ChiselStage()
Value Members
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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def
==(arg0: Any): Boolean
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def
asInstanceOf[T0]: T0
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clone(): AnyRef
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final
def
emitChirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to a CHIRRTL string
Convert a Chisel module to a CHIRRTL string
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel
- returns
a string containing the Verilog output
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final
def
emitFirrtl(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to a FIRRTL string
Convert a Chisel module to a FIRRTL string
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel
- returns
a string containing the Verilog output
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final
def
emitVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String
Convert a Chisel module to Verilog
Convert a Chisel module to Verilog
- gen
a call-by-name Chisel module
- args
additional command line arguments to pass to Chisel param annotations additional annotations to pass to Chisel
- returns
a string containing the Verilog output
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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final
def
execute(args: Array[String], annotations: AnnotationSeq): AnnotationSeq
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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final
def
invalidates(a: Phase): Boolean
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final
def
isInstanceOf[T0]: Boolean
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val
logger: Logger
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lazy val
name: String
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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def
notifyAll(): Unit
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def
optionalPrerequisiteOf: Seq[Dependency[Phase]]
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def
optionalPrerequisites: Seq[Dependency[Phase]]
- Definition Classes
- DependencyAPI
- final lazy val phaseManager: PhaseManager { val wrappers: Seq[firrtl.options.Phase => firrtl.options.phases.DeletedWrapper] }
-
def
prerequisites: Seq[Dependency[Phase]]
- Definition Classes
- DependencyAPI
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def
run(annotations: AnnotationSeq): AnnotationSeq
- Definition Classes
- ChiselStage → Stage
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val
shell: Shell
- Definition Classes
- ChiselStage → Stage
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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- val targets: Seq[Dependency[Phase]]
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def
toString(): String
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final
def
transform(annotations: AnnotationSeq): AnnotationSeq
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- Stage → TransformLike
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.