Packages

  • package root

    This is the documentation for Chisel.

    This is the documentation for Chisel.

    Package structure

    The chisel3 package presents the public API of Chisel. It contains the concrete core types UInt, SInt, Bool, FixedPoint, Clock, and Reg, the abstract types Bits, Aggregate, and Data, and the aggregate types Bundle and Vec.

    The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.

    Utility objects and methods are found in the util package.

    The testers package defines the basic interface for chisel testers.

    Definition Classes
    root
  • package chisel3
    Definition Classes
    root
  • package aop
    Definition Classes
    chisel3
  • package experimental
    Definition Classes
    chisel3
  • BackendCompilationUtilities
  • emitVerilog
  • getVerilogString
  • package stage
    Definition Classes
    chisel3
  • package testers

    The testers package provides the basic interface for chisel testers.

    The testers package provides the basic interface for chisel testers.

    Definition Classes
    chisel3
  • package util

    The util package provides extensions to core chisel for common hardware components and utility functions

    The util package provides extensions to core chisel for common hardware components and utility functions

    Definition Classes
    chisel3
o

chisel3

getVerilogString

object getVerilogString

Source
verilog.scala
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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  3. final def ==(arg0: Any): Boolean
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  4. def apply(gen: => RawModule, args: Array[String] = Array.empty, annotations: AnnotationSeq = Seq.empty): String

    Returns a string containing the Verilog for the module specified by the target accepting arguments and annotations

    Returns a string containing the Verilog for the module specified by the target accepting arguments and annotations

    gen

    the module to be converted to Verilog

    args

    arguments to be passed to the compiler

    annotations

    annotations to be passed to the compiler

    returns

    a string containing the Verilog for the module specified by the target

  5. def apply(gen: => RawModule): String

    Returns a string containing the Verilog for the module specified by the target.

    Returns a string containing the Verilog for the module specified by the target.

    gen

    the module to be converted to Verilog

    returns

    a string containing the Verilog for the module specified by the target

  6. final def asInstanceOf[T0]: T0
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  7. def clone(): AnyRef
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  8. final def eq(arg0: AnyRef): Boolean
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  10. final def getClass(): Class[_ <: AnyRef]
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  11. def hashCode(): Int
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  12. final def isInstanceOf[T0]: Boolean
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  13. final def ne(arg0: AnyRef): Boolean
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  15. final def notifyAll(): Unit
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  16. final def synchronized[T0](arg0: => T0): T0
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  17. def toString(): String
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  18. final def wait(arg0: Long, arg1: Int): Unit
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  19. final def wait(arg0: Long): Unit
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  20. final def wait(): Unit
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  1. def finalize(): Unit
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