class BasicTester extends Module
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- new BasicTester()
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- final def !=(arg0: Any): Boolean
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- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: T): T
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- def _bindIoInPlace(iodef: Data): Unit
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- var _closed: Boolean
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- def _compatAutoWrapPorts(): Unit
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- final def asInstanceOf[T0]: T0
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- def circuitName: String
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- final val clock: Clock
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- def clone(): AnyRef
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- val compileOptions: CompileOptions
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- def desiredName: String
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- final def eq(arg0: AnyRef): Boolean
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- def equals(that: Any): Boolean
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- HasId → AnyRef → Any
- def finish(): Unit
The finish method provides a hook that subclasses of BasicTester can use to alter a circuit after their constructor has been called.
The finish method provides a hook that subclasses of BasicTester can use to alter a circuit after their constructor has been called. For example, a specialized tester subclassing BasicTester could override finish in order to add flow control logic for a decoupled io port of a device under test
- final def getClass(): Class[_ <: AnyRef]
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- protected[chisel3]
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- def hasSeed: Boolean
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- def hashCode(): Int
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- def instanceName: String
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- val io: Bundle
- final def isInstanceOf[T0]: Boolean
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- final lazy val name: String
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- def nameIds(rootClass: Class[_]): HashMap[HasId, String]
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- final def notify(): Unit
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- final def notifyAll(): Unit
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- def parentModName: String
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- def parentPathName: String
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- def popCount(n: Long): Int
- def portsContains(elem: Data): Boolean
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- def portsSize: Int
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- final val reset: Reset
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- def stop()(implicit sourceInfo: SourceInfo): Unit
Ends the test reporting success.
Ends the test reporting success.
Does not fire when in reset (defined as the encapsulating Module's reset). If your definition of reset is not the encapsulating Module's reset, you will need to gate this externally.
- def suggestName(seed: => String): BasicTester.this.type
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- final def synchronized[T0](arg0: => T0): T0
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- final def toAbsoluteTarget: IsModule
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- def toString(): String
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- final def toTarget: ModuleTarget
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- final def wait(arg0: Long, arg1: Int): Unit
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- final def wait(arg0: Long): Unit
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- final def wait(): Unit
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Deprecated Value Members
- def finalize(): Unit
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- @throws(classOf[java.lang.Throwable]) @Deprecated
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- lazy val getPorts: Seq[Port]
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- RawModule
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- @deprecated
- Deprecated
(Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6
- def override_clock: Option[Clock]
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.