FPGABackend

Value Members

1. final def !=(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

2. final def !=(arg0: Any): Boolean

   Definition Classes

   Any

3. final def ##(): Int

   Definition Classes

   AnyRef → Any

4. final def ==(arg0: AnyRef): Boolean

   Definition Classes

   AnyRef

5. final def ==(arg0: Any): Boolean

   Definition Classes

   Any

6. def W0Wtransform(): Unit

   Definition Classes

   Backend

7. def addBindings: Unit

   Definition Classes

   Backend

8. def addClocksAndResets: Unit

   Definition Classes

   Backend

9. def addDefaultResets: Unit

   Definition Classes

   Backend

10. val analyses: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

11. final def asInstanceOf[T0]: T0

    Definition Classes

    Any

12. def asValidName(name: String): String

    Definition Classes

    Backend

13. def assignClockAndResetToModules: Unit

    Definition Classes

    Backend

14. def checkModuleResolution: Unit

    Definition Classes

    Backend

15. def checkPorts: Unit

    Definition Classes

    Backend

16. def clone(): AnyRef

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

17. def collectNodesIntoComp(mod: Module): Unit

    Definition Classes

    Backend

18. val compIndices: HashMap[String, Int]

    Definition Classes

    VerilogBackend

19. def compile(c: Module, flags: String): Unit

    Definition Classes

    VerilogBackend → Backend

20. def computeMemPorts(mod: Module): Unit

    Definition Classes

    Backend

21. def connectResets: Unit

    Definition Classes

    Backend

22. def createOutputFile(name: String): FileWriter

    Definition Classes

    FileSystemUtilities

23. def depthString(depth: Int): String

    Definition Classes

    Backend

24. def doCompile(top: Module, out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

25. def elaborate(c: Module): Unit

    Definition Classes

    VerilogBackend → Backend

26. def emitAssert(a: Assert): String

    Definition Classes

    VerilogBackend

27. def emitChildren(top: Module, defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], out: FileWriter, depth: Int): Unit

    Definition Classes

    VerilogBackend

28. def emitDec(node: Node): String

    Definition Classes

    VerilogBackend → Backend

29. def emitDecBase(node: Node, wire: String = "wire"): String

    Definition Classes

    VerilogBackend

30. def emitDecReg(node: Node): String

    Definition Classes

    VerilogBackend

31. def emitDecs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

32. def emitDef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

33. def emitDef(c: Module): String

    Definition Classes

    VerilogBackend

34. def emitDefs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

35. def emitInit(node: Node): String

    Definition Classes

    VerilogBackend

36. def emitInits(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

37. def emitModuleText(c: Module): String

    Definition Classes

    VerilogBackend

38. def emitPortDef(m: MemAccess, idx: Int): String

    Definition Classes

    VerilogBackend

39. def emitPrintf(p: Printf): String

    Definition Classes

    VerilogBackend

40. def emitRef(node: Node): String

    Definition Classes

    VerilogBackend → Backend

41. def emitRef(c: Module): String

    Definition Classes

    Backend

42. def emitReg(node: Node): String

    Definition Classes

    VerilogBackend

43. def emitRegs(c: Module): StringBuilder

    Definition Classes

    VerilogBackend

44. def emitTmp(node: Node): String

    Definition Classes

    VerilogBackend → Backend

45. def emitWidth(node: Node): String

    Definition Classes

    VerilogBackend

46. val emittedModules: HashSet[String]

    Definition Classes

    VerilogBackend

47. def ensureDir(dir: String): String

    Ensures a directory *dir* exists on the filesystem.

    Ensures a directory *dir* exists on the filesystem.

    Definition Classes

    FileSystemUtilities

48. final def eq(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

49. def equals(arg0: Any): Boolean

    Definition Classes

    AnyRef → Any

50. def execute(c: Module, walks: ArrayBuffer[(Module) ⇒ Unit]): Unit

    Definition Classes

    Backend

51. def extractClassName(comp: Module): String

    Definition Classes

    Backend

52. def finalize(): Unit

    Attributes

    protected[java.lang]

    Definition Classes

    AnyRef

    Annotations

    @throws( classOf[java.lang.Throwable] )

53. def findCombLoop: Unit

    Definition Classes

    Backend

54. def findConsumers(mod: Module): Unit

    Definition Classes

    Backend

55. def findGraphDims: (Int, Int, Int)

    Definition Classes

    Backend

56. def flattenAll: Unit

    Definition Classes

    Backend

57. def flushModules(defs: LinkedHashMap[String, LinkedHashMap[String, ArrayBuffer[Module]]], level: Int): Unit

    Definition Classes

    VerilogBackend

58. def forceMatchingWidths: Unit

    Definition Classes

    Backend

59. def fullyQualifiedName(m: Node): String

    Definition Classes

    Backend

60. def gatherClocksAndResets: Unit

    Definition Classes

    Backend

61. def genHarness(c: Module, name: String): Unit

    Definition Classes

    VerilogBackend

62. def genIndent(x: Int): String

    Attributes

    protected

    Definition Classes

    Backend

63. final def getClass(): Class[_]

    Definition Classes

    AnyRef → Any

64. def harnessAPIs(mainClk: Clock, clocks: ListSet[Clock], resets: List[Bool]): String

    Definition Classes

    VerilogBackend

65. def harnessBase(mainClk: Clock, resets: List[Bool], scanNodes: Array[Bits], printNodes: Array[Bits]): String

    Definition Classes

    VerilogBackend

66. def hashCode(): Int

    Definition Classes

    AnyRef → Any

67. def inferAll(mod: Module): Int

    Definition Classes

    Backend

68. def isBitsIo(node: Node, dir: IODirection): Boolean

    Nodes which are created outside the execution trace from the toplevel component constructor (i.

    Nodes which are created outside the execution trace from the toplevel component constructor (i.e. through the () => Module(new Top()) ChiselMain argument) will have a component field set to null. For example, genMuxes, forceMatchWidths and transforms (all called from Backend.elaborate) create such nodes.

    This method walks all nodes from all component roots (outputs, debugs). and reassociates the component to the node both ways (i.e. in Driver.nodes and Node.component).

    We assume here that all nodes at the components boundaries (io) have a non-null and correct node/component association. We further assume that nodes generated in elaborate are inputs to a node whose component field is set.

    Implementation Node: At first we did implement *collectNodesIntoComp* to handle a single component at a time but that did not catch the cases where Regs are passed as input to sub-module without being tied to an output of *this.component*.

    Definition Classes

    Backend

69. def isEmittingComponents: Boolean

    Definition Classes

    VerilogBackend → Backend

70. def isInObject(n: Node): Boolean

    Definition Classes

    Backend

71. final def isInstanceOf[T0]: Boolean

    Definition Classes

    Any

72. val keywords: Set[String]

    Definition Classes

    VerilogBackend → Backend

73. def lowerNodes(mod: Module): Unit

    Definition Classes

    Backend

74. def markComponents: Unit

    Definition Classes

    Backend

75. val memConfs: HashMap[String, String]

    Definition Classes

    VerilogBackend

76. def nameAll(): Unit

    Definition Classes

    Backend

77. def nameBindings: Unit

    Definition Classes

    Backend

78. def nameRsts: Unit

    Definition Classes

    Backend

79. val nameSpace: HashSet[String]

    Definition Classes

    Backend

80. final def ne(arg0: AnyRef): Boolean

    Definition Classes

    AnyRef

81. val needsLowering: Set[String]

    Definition Classes

    VerilogBackend → Backend

82. final def notify(): Unit

    Definition Classes

    AnyRef

83. final def notifyAll(): Unit

    Definition Classes

    AnyRef

84. def printStack: Unit

    Prints the call stack of Component as seen by the push/pop runtime.

    Prints the call stack of Component as seen by the push/pop runtime.

    Attributes

    protected

    Definition Classes

    Backend

85. def pruneUnconnectedIOs(m: Module): Unit

    Definition Classes

    Backend

86. def removeTypeNodes(mod: Module): Int

    All classes inherited from Data are used to add type information and do not represent logic itself.

    All classes inherited from Data are used to add type information and do not represent logic itself.

    Definition Classes

    Backend

87. def sortComponents: Unit

    Definition Classes

    Backend

88. final def synchronized[T0](arg0: ⇒ T0): T0

    Definition Classes

    AnyRef

89. def synthesizeable(node: Node): Boolean

    Definition Classes

    VerilogBackend

90. def toString(): String

    Definition Classes

    AnyRef → Any

91. val transforms: ArrayBuffer[(Module) ⇒ Unit]

    Definition Classes

    Backend

92. def verifyAllMuxes: Unit

    Definition Classes

    Backend

93. final def wait(): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

94. final def wait(arg0: Long, arg1: Int): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )

95. final def wait(arg0: Long): Unit

    Definition Classes

    AnyRef

    Annotations

    @throws( ... )