object
chiselMain
Value Members
-
final
def
!=(arg0: AnyRef): Boolean
-
final
def
!=(arg0: Any): Boolean
-
final
def
##(): Int
-
final
def
==(arg0: AnyRef): Boolean
-
final
def
==(arg0: Any): Boolean
-
def
apply[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T]): T
-
def
apply[T <: Module](args: Array[String], gen: () ⇒ T): T
-
final
def
asInstanceOf[T0]: T0
-
def
clone(): AnyRef
-
final
def
eq(arg0: AnyRef): Boolean
-
def
equals(arg0: Any): Boolean
-
def
finalize(): Unit
-
final
def
getClass(): Class[_]
-
def
hashCode(): Int
-
final
def
isInstanceOf[T0]: Boolean
-
final
def
ne(arg0: AnyRef): Boolean
-
final
def
notify(): Unit
-
final
def
notifyAll(): Unit
-
def
run[T <: Module](args: Array[String], gen: () ⇒ T, ftester: (T) ⇒ Tester[T]): T
-
def
run[T <: Module](args: Array[String], gen: () ⇒ T): T
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
-
def
toString(): String
-
val
unwrapped: Boolean
-
final
def
wait(): Unit
-
final
def
wait(arg0: Long, arg1: Int): Unit
-
final
def
wait(arg0: Long): Unit
-
val
wrapped: Boolean
Inherited from AnyRef
Inherited from Any
_chiselMain_ behaves as if it constructs an execution tree from the constructor of a sub class of Module which is passed as a parameter. That execution tree is simplified by aggregating all calls which are not constructors of a Module instance into the parent which is. The simplified tree (encoded through _Driver.children_) forms the basis of the generated verilog. Each node in the simplified execution tree is a _Module_ instance from which a verilog module is textually derived. As an optimization, _Backend_ classes output modules which are textually equivalent only once and update a _Module_ instance's _moduleName_ accordingly.